IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 33

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

4.3 SPI-3 ingress to SPI-3 egress datapath
packet fragment buffers is forwarded to the associated packet fragment proces-
sor. The purpose of the SPI-3 redirect is to enable per-LP flows between
physical interfaces SPI-3 A and SPI-3 B; as well as between SPI-3 C and SPI-
3 D. Other flows between SPI-3 ports are not allowed; i.e., between A and A,
A and C, A and D, B and B, B and C, B and D, C and C, and D and D.
the device.
SPI-3 path is between an LP on one SPI-3 to the paired SPI-3. Data enters on
the SPI-3 interface in fragments. Fragments are of equal length except the last
fragment of a packet which may be shorter. The LP address is in-band with the
data. The packet fragment enters an ingress buffer. SPI-3 LP address, error
information, SOP, and EOP information is are stored with the fragment. The LP
address is mapped to a LID. The fragment is stored in buffer segment pool per-
LID-allocated memory space.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The SPI-3 redirect buffer can store SPI-3 packet fragments. The status of the
The following is a description of the path taken by a fragment of data through
SPI-3 modules are implemented in pairs (ports A & B or C & D). A SPI-3 to
Min: 19.44MHz
Min: 19.44MHz
Max: 133MHz
Max: 133MHz
8 bit / 32 bit
8 bit / 32 bit
SPI-3
SPI-3
Figure 21. SPI-3 ingress to SPI-3 egress datapath
JTAG
LID Counters Memory
LID Counters Memory
Memory
SPI-3 /
LID map
uproc
Memory
LID map
SPI-3 /
Main
Main
B
A
33
and the PFP decides to send a LID to the associated SPI-3 egress port. The
SPI-3 packet fragment processor chooses the next LP. The choice of LP is
dependent on status of the LP and availability of a complete fragment. Data is
moved to an egress buffer along with the SPI-3 LP address, error information,
SOP, and EOP information. Data is transmitted in packet fragments over a SPI-
3 interface.
mappings from a SPI-3 LP to a SPI-3 LP where not provided, and from a SPI-
4 to a SPI-4 LP. However these paths are limited by the bandwidth of the
microprocessor interface.
interface to its paired SPI-3 interface. For the SPI-3 redirect, the LID connecting
associated port pairs must be the same in both directions.
Chip Counters Memory
The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,
The paths to and from the microprocessor interface can be used to perform
The diagram below shows the datapath through the device from a SPI-3
SPI-4 /
LID map
6370 drw14
Max: 400 MHz
Min: 80 MHz
INDUSTRIAL TEMPERATURE RANGE
SPI-4.2
APRIL 10, 2006