IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 8

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

Exchange between secure traffic, clear traffic, 10G NPU and co-processor
switching capabilities intended for use in VPN firewall cards, Ethernet transport,
and multi-service switches. The SPI-3 and SPI-4 interfaces are defined by the
Optical Internetworking Forum (OIF).
between network processor units, multi-gigabit framers and PHYs, and switch
fabric interface devices.
Data Path Overview
the device.
the quad SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to quad
SPI-3 egress path. SPI-3 and SPI-4 burst sizes are separately configurable.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The IDT88P8344 device is a quad SPI-3 to single SPI-4 exchange with
The device can be used as an exchange, a switch, or an aggregation device
Figure 2. Data Path Diagram shows an overview of the data path through
In normal operation, there are two paths through the IDT88P8344 device:
In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the
Secure Traffic
Clear Traffic
SPI-3
SPI-3
SPI-3
SPI-3
Figure 1. Typical application: NPU, PHY, and co-processor
Transceiver
Transceiver
Multi-port
Multi-port
I/F
I/F
I/F
I/F
Ethernet
Ethernet
SPI-3 ingress to SPI-4 egress
SPI-4 ingress to SPI-3 egress
Memory
Memory
Memory
Memory
Figure 2. Data path diagram
SPI-3
SPI-3
IDT88P8344
8
SPI-3 interface and are received by the SPI-3 interface block. The fragments
are mapped to a SPI-4 address and stored in memory allocated at the SPI-3
level until such a time that the SPI-3 to SPI-4 packet fragment processor
determines that they are to be transmitted on the SPI-4 interface. The data is
transferred in bursts, in line with the OIF SPI-4 implementation agreement, to
the SPI-4 interface block, and are transmitted on the SPI-4 interface.
4 interface and are received by the SPI-4 interface block. The SPI-4 address
is translated to a SPI-3 address, and the data contained in the bursts are stored
in memory allocated at the SPI-3 level until such a time that the SPI-4 to SPI-
3 packet fragment processor determines that they are to be transmitted on the
SPI-3 interface. The data is transferred in packet fragments, in line with the OIF
SPI-3 implementation agreement, to the SPI-3 interface block, and are trans-
mitted on the SPI-3 interface.
section of this document.
In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-
These and additional data paths are described in more detail in the data path
I/F
6370 drw03
SPI-4
SPI-3
SPI-3
SPI-4
Memory
Co-Processor
Co-Processor
INDUSTRIAL TEMPERATURE RANGE
NPU
Additional
or PHY
6370 drw02
Processor
Memory
Control
PCI
APRIL 10, 2006