EPC16xxx Altera, EPC16xxx Datasheet - Page 8

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Functional Description
Figure 2–2. FPP Configuration
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
2–8
Configuration Handbook, Volume 2
The V
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to V
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus
OE pull-ups on configuration device option when generating programming files.
For PORSEL, PGM[], and EXCLK pin connections, refer to
In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15
to F-A15, C-A16 to F-A16, and BYTE# to V
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V
GND, and WP# to V
Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
(6)
Figure
N.C.
CC
n
should be connected to the same supply voltage as the configuration device.
2–2:
MSEL
nCEO
APEX II Device
Stratix Series
CC
CC
CONF_DONE
.
or
either directly or through a resistor.
DATA[7..0]
nCONFIG
nSTATUS
Multiple FPGAs can be configured using a single enhanced configuration
device in FPP mode. In this mode, multiple Stratix series and/or APEX II
FPGAs are cascaded together in a daisy chain.
DCLK
nCE
®
II software. To turn off the internal pull-up resistors, check the Disable nCS and
V
CC
(3)
(1)
GND
V
CC
CC
. Additionally, you must make the following pin connections in both
(3)
(1)
(1)
GND
V
CC
Enhanced Configuration
BYTE# (5)
WP#
TM1
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
WE#C
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF (2)
TMO
Table
(3)
(3)
2–9.
Device
PGM[2..0]
DQ[15..0]
PORSEL
A[20..0]
RY/BY#
EXCLK
VCCW
WE#F
A0-F
A1-F
A15-F
A16-F
RP#F
OE#
CE#
V
CC
(4)
(4)
(4)
(1)
N.C.
N.C.
N.C.
N.C.
N.C.
Altera Corporation
August 2005
CC
, TM0 to