EPC16xxx Altera, EPC16xxx Datasheet - Page 21

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Pin Description
Altera Corporation
August 2005
DATA[7..0] Output
DCLK
nCS
nINIT_CONF Open-Drain Output
OE
Table 2–7. Configuration Interface Pins
Pin Name
Output
Input
Open-Drain
Bidirectional
Pin Type
Tables 2–7
These tables include configuration interface pins, external flash interface
pins, JTAG interface pins, and other pins.
This is the configuration data output bus. DATA changes on each falling
edge of DCLK. DATA is latched into the FPGA on the rising edge of DCLK.
The DCLK output pin from the enhanced configuration device serves as
the FPGA configuration clock. DATA is latched by the FPGA on the rising
edge of DCLK.
The nCS pin is an input to the enhanced configuration device and is
connected to the FPGA’s CONF_DONE signal for error detection after all
configuration data is transmitted to the FPGA. The FPGA will always drive
nCS and OE low when nCONFIG is asserted. This pin contains a
programmable internal weak pull-up resistor that can be disabled/enabled
in the Quartus II software through the Disable nCS and OE pull-ups on
configuration device option.
The nINIT_CONF pin can be connected to the nCONFIG pin on the FPGA
to initiate configuration from the enhanced configuration device via a
private JTAG instruction. This pin contains an internal weak pull-up
resistor that is always active. The INIT_CONF pin does not need to be
connected if its functionality is not used. If nINIT_CONF is not used,
nCONFIG must be pulled to V
resistor.
This pin is driven low when POR is not complete. A user-selectable 2-ms
or 100-ms counter holds off the release of OE during initial power up to
permit voltage levels to stabilize. POR time can be extended by externally
holding OE low. OE is connected to the FPGA nSTATUS signal. After the
enhanced configuration device controller releases OE, it waits for the
nSTATUS-OE line to go high before starting the FPGA configuration
process. This pin contains a programmable internal weak pull-up resistor
that can be disabled/enabled in the Quartus II software through the
Disable nCS and OE pull-ups on configuration device option.
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
through
2–9
describe the enhanced configuration device pins.
CC
Description
either directly or through a pull-up
Configuration Handbook, Volume 2
2–21