EPC16xxx Altera, EPC16xxx Datasheet - Page 31

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Operating
Conditions
Altera Corporation
August 2005
Notes to
(1)
(2)
(3)
(4)
t
t
f
t
t
t
t
t
t
V
V
I
I
P
T
T
T
RE
LOE
ECLK
ECLK
ECLKH
ECLKL
ECLKR
ECLKF
POR
MAX
OUT
Table 2–13. Enhanced Configuration Device Configuration Parameters (Part 2 of 2)
Table 2–14. Enhanced Configuration Device Absolute Maximum Rating
AMB
STG
J
CC
I
D
Symbol
(3)
(4)
To calculate t
This parameter is used for CRC error detection by the FPGA.
This parameter is used for CONF_DONE error detection by the enhanced configuration device.
The FPGA V
POR.
Symbol
Table
2–13:
DCLK rising edge to OE
OE assert time to assure reset
EXCLK input frequency
EXCLK input period
EXCLK input duty cycle high time
EXCLK input duty cycle low time
EXCLK input rise time
EXCLK input fall time
POR time
CCINT
OH
, use the following equation: t
Supply voltage
DC input voltage
DC V
DC output current, per pin
Power dissipation
Storage temperature
Ambient temperature
Junction temperature
ramp time should be less than 1-ms for 2-ms POR, and it should be less than 70 ms for 100-ms
CC
Parameter
Parameter
or ground current
Tables 2–14
ratings, recommended operating conditions, DC operating conditions,
supply current values, and pin capacitance data for the enhanced
configuration devices.
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
through
OH
With respect to ground
With respect to ground
No bias
Under bias
Under bias
= 0.5 (DCLK period) - 2.5 ns.
2–18
40% duty cycle
40% duty cycle
40% duty cycle
Condition
Condition
133 MHz
133 MHz
100 ms
provide information on absolute maximum
2 ms
Configuration Handbook, Volume 2
3.375
3.375
Min
7.5
60
60
70
1
Min
-0.5
-0.5
-25
-65
-65
100
Typ
2
Max
100
360
150
135
135
4.6
3.6
25
Max
133
120
3
3
3
Unit
mW
mA
mA
MHz
Unit
C
V
V
C
C
ms
ms
ns
ns
ns
ns
ns
ns
ns
2–31