EPC16xxx Altera, EPC16xxx Datasheet - Page 24

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Power-On Reset (POR)
Power-On Reset
(POR)
2–24
Configuration Handbook, Volume 2
TDI
TDO
TCK
TMS
PGM[2..0]
EXCLK
PORSEL
TM0
TM1
Table 2–9. JTAG Interface Pins and Other Required Controller Pins
Pin Name
Pin Type
Output
Input
Input
Input
Input
Input
Input
Input
Input
The POR circuit keeps the system in reset until power supply voltage
levels have stabilized. The POR time consists of the V
user programmable POR delay counter. When the supply is stable and
the POR counter expires, the POR circuit releases the OE pin. The POR
time can be further extended by an external device by driving the OE pin
low.
1
This is the JTAG data input pin.
Connect this pin to V
This is the JTAG data output pin.
Do not connect this pin if the JTAG circuitry is not used (leave floating).
This is the JTAG clock pin.
Connect this pin to GND if the JTAG circuitry is not used.
This is the JTAG mode select pin.
Connect this pin to V
These three input pins select one of the eight pages of configuration data
to configure the FPGA(s) in the system.
Connect these pins on the board to select the page specified in the
Quartus II software when generating the enhanced configuration device
POF. PGM[2] is the MSB. Default selection is page 0; PGM[2..0]=000.
These pins must not be left floating.
Optional external clock input pin that can be used to generate the
configuration clock (DCLK).
When an external clock source is not used, connect this pin to a valid logic
level (high or low) to prevent a floating input buffer.
This pin selects a 2-ms or 100-ms POR counter delay during power up.
When PORSEL is low, POR time is 100-ms. When PORSEL is high, POR
time is 2 ms.
This pin must be connected to a valid logic level.
For normal operation, this test pin must be connected to GND.
For normal operating, this test pin must be connected to V
Do not execute JTAG or ISP instructions until POR is complete.
CC
CC
if the JTAG circuitry is not used.
if the JTAG circuitry is not used.
Description
CC
Altera Corporation
ramp time and a
CC
.
August 2005