EPC16xxx Altera, EPC16xxx Datasheet - Page 28

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EPC16xxx

Manufacturer Part Number
EPC16xxx
Description
(EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
Manufacturer
Altera
Datasheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Figure 2–6. JTAG Timing Waveforms
2–28
Configuration Handbook, Volume 2
Captured
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
t
JCH
You can also program the enhanced configuration devices using the
Quartus II software, the Altera Programming Unit (APU), and the
appropriate configuration device programming adapter.
shows which programming adapter to use with each enhanced
configuration device.
The enhanced configuration device provides JTAG BST circuitry that
complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-
scan testing can be performed before or after configuration, but not
during configuration.
Figure 2–6
EPC16
EPC8
EPC4
t
JSZX
Table 2–11. Table 10. Programming Adapters
t
JPZX
t
JCP
t
JSSU
Device
t
JCL
shows the timing requirements for the JTAG signals.
t
JSH
t
t
JPCO
JSCO
88-pin Ultra FineLine BGA
100-pin PQFP
100-pin PQFP
100-pin PQFP
t
JPSU
Package
t
t
JPH
JSXZ
t
JPXZ
PLMUEPC-88
PLMQEPC-100
PLMQEPC-100
PLMQEPC-100
Altera Corporation
Table 2–11
Adapter
August 2005

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