EPC16xxx Altera, EPC16xxx Datasheet - Page 30

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EPC16xxx

Manufacturer Part Number
EPC16xxx
Description
(EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
Manufacturer
Altera
Datasheet
Timing Information
Timing
Information
Figure 2–7. Configuration Timing Waveform Using an Enhanced Configuration Device
Notes to
(1)
(2)
2–30
Configuration Handbook, Volume 2
f
t
t
t
t
t
t
t
t
DCLK
DCLK
HC
LC
CE
OE
OH
CF
DF
Table 2–13. Enhanced Configuration Device Configuration Parameters (Part 1 of 2)
Symbol
(2)
(2)
The enhanced configuration device will drive DCLK low after configuration.
The enhanced configuration device will DATA[] high after configuration.
nCS/CONF_DONE
nINIT_CONF or
VCC/nCONFIG
Figure
OE/nSTATUS
INIT_DONE
User I/O
2–7:
DCLK frequency
DCLK period
DCLK duty cycle high time
DCLK duty cycle low time
OE to first DCLK delay
OE to first DATA available
DCLK rising edge to DATA change
OE assert to DCLK disable delay
OE assert to DATA disable delay
DCLK
DATA
f
Driven High
t
LOE
Parameter
t
OE
Figure 2–7
enhanced configuration device.
Table 2–13
configuration devices.
For flash memory (external flash interface) timing information, please
refer to the corresponding flash data sheet on the Altera web site (Sharp
LHF16J06 for EPC16 devices and Micron MT28F400B3 for EPC4 devices).
t
CE
Tri-State
bit/byte
1
bit/byte
t
2
HC
shows the configuration timing waveform when using an
defines the timing parameters when using the enhanced
t
LC
40% duty cycle
40% duty cycle
40% duty cycle
Condition
bit/byte
n
Tri-State
Min
277
277
15
40
40
(1)
6
6
Typ
User Mode
Altera Corporation
Max
66.7
(1)
(2)
August 2005
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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