EPC16xxx Altera, EPC16xxx Datasheet - Page 4

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Functional Description
2–4
Configuration Handbook, Volume 2
1
Other user programmable features include:
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FPGA Configuration
FPGA configuration is managed by the configuration controller chip.
This process includes reading configuration data from the flash memory,
decompressing it if necessary, transmitting configuration data via the
appropriate DATA[] pins, and handling errors conditions.
After POR, the controller determines the user-defined configuration
options by reading its option bits from the flash memory. These options
include the configuration scheme, configuration clock speed,
decompression, and configuration page settings. The option bits are
stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the
internal flash interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, it checks if the FPGA is ready
to accept configuration data by monitoring the nSTATUS and
CONF_DONE lines. When the FPGA is ready (nSTATUS is high and
CONF_DONE is low), the controller begins data transfer using the DCLK
and DATA[] output pins. The controller selects the configuration page to
be transmitted to the FPGA(s) by sampling its PGM[2..0] pins after POR
or reset.
The function of the configuration unit is to transmit decompressed data
to the FPGA, depending on the configuration scheme. The enhanced
configuration device supports four concurrent configuration modes, with
n = 1, 2, 4, or 8 (where n is the number of bits that are sent per DCLK cycle
on the DATA[n] lines). The value n=1 corresponds to the traditional PS
configuration scheme. The values n=2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively.
Additionally, the FPGA can be configured in FPP mode, where eight bits
of DATA are clocked into the FPGA per DCLK cycle. Depending on the
configuration bus width (n), the circuit shifts uncompressed
configuration data to the valid DATA[n] pins. Unused DATA[] pins drive
low.
Real-time decompression of configuration data
Programmable configuration clock (DCLK)
Flash ISP
Programmable power-on-reset delay (PORSEL)
For more information on Stratix Remote System Configuration,
refer to the Using Remote System Configuration with Stratix &
Stratix GX Devices chapter of the Stratix Device Handbook.
Altera Corporation
August 2005