HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 31

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

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4.2
The registers RAM_ADR_H, RAM_ADR_L and RAM_DATA can be used for direct accesses to the
internal FIFO-RAM.
The FIFOs are located in the address range from 000h to 3FFh. Bits 2..0 of the address select the FIFO
number, bits 10..4 are used to address the FIFO data.
Before reading / writing data from / to a memory region all FIFOs using this region must be disabled.
Name
CIRM
F_CROSS
F_MODE
INC_RES_F
[FIFO#]
RAM_ADR_L
RAM_ADR_H
RAM_DATA
FIFO, interrupt, status and control registers
Addr.
0Dh
0Ah
0Bh Select bit order for FIFO data
0Eh
00h
08h
09h
'0'
'1'
Bits
2..0
7..4
6..0
7..2
7..0
2..0
5..3
7..0
3
0
1
2
3
4
5
6
7
7
0
1
6
7
normal bit order (LSB first, reset default)
reverse bit order (MSB first)
r/w Function
r/w read/write RAM data
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
soft reset
The reset is active until the bit is cleared.
'0' deactivate reset (reset default)
'1' activate reset
B1-transmit
B1-receive
B2-transmit
B2- receive
D-transmit
D- receive
PCM-transmit
PCM-receive
Channel Select Mode enable (CSM)
reset selected FIFO ('1'=reset FIFO)
'1' reset address
This bit is automatically cleared.
'1' increment address after each read or write access to
FIFOs should be disabled before accessing the RAM directly.
unused, must be '0'
unused, must be '0'
must be '0'
increment F-counter of selected FIFO ('1'=increment)
unused, should be '0'
Address bits 7..0 for direct RAM access
Address bits 10..8 for direct RAM access
must be '0'
RAM_DATA
Cologne
Chip