HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 19

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

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3.3
You can switch off HDLC operation for each B-channel independently. There is one bit for each B-
channel in the CON_HDLC control register. If this bit is set data in the FIFO is sent directly to the S/T or
PCM bus interface and data from the S/T or PCM bus interface is sent directly to the FIFO.
The FIFOs should be empty when switching into transparent mode.
If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte in
the FIFO memory is repeated until there is new data. If the last data byte which was written to the
selected FIFO should be repeated the last byte must be written without increment of Z-counter
(FIF_DATA register, address 84h).
In receive channels there is no check on flags or correct CRCs and no status byte is added.
The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with
HDLC-flags. The data is just the same as it comes from the S/T or PCM bus interface or is sent to this.
Send and receive transparent data can be handled in two ways. The usual way is transporting B-channel
data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit
order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting the
corresponding bit in the F_CROSS register.
Transparent mode of HFC-S mini
Cologne
Chip