HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 18

Manufacturer Part Number

HFC-Smini

Description

Manufacturer

Cologne Chip AG

Datasheet

1.HFC-SMINI.pdf (78 pages)

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3.2.2 FIFO initialization

After reset all FIFOs are disabled. To enable a FIFO at least one of bits[4:1] of the CON_HDLC register

for the corresponding FIFO must be set to '1'.

For D-channel FIFOs the inter frame fill bit (bit 0 of CON_HDLC register) must be set to '1'. The

HDLC_PAR register must be set to 02h ('0000 0010').

3.2.3 FIFO reset

All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET.

Then the result is Z1 = Z2 = 7Fh and F1 = F2 = 07h.

The same initialisation is done if the bit 3 in the CIRM register is set (soft reset).

Single FIFOs can be reset by setting bit 1 of INC_RES_F register.

Cologne

Chip