HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 20

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

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3.4
For the data processing of the HFC-S mini you must distinguish between FIFOs, CHANNELs and
SLOTs.
The FIFOs are buffers between the microprocessor interface and the data interfaces PCM and/or S/T.
The HDLC controllers are located on the non host bus side of the FIFOs.
The CHANNELs are either mapped to the data channels on the S/T interface (then the CHANNEL
selects the S/T channel as shown in Table 3) or they can be connected to arbitrary timeslots on the PCM
interface. SLOTs are 8 bit timeslots on the PCM interface.
The following values (registers) characterise FIFOs, CHANNELs and SLOTs:
FIFO:
CHANNEL:
SLOT:
Even numbers (LSB = '0') always belong to a transmit FIFO, transmit CHANNEL (see also: Table 3).
Odd numbers (LSB = '1') always belong to a receive FIFO, receive CHANNEL (see also: Table 3).
In Simple Mode (F_MODE register bit 7 = '0', SM) the CHANNEL number equals the FIFO number. But
it is possible to connect each FIFO to a PCM timeslot instead of the S/T interface in this mode (see table
below).
Table 2: Possible connections of FIFOs and CHANNELs in Simple Mode (SM)
(FIFO#, bits 2..0)
FIFO-No.
'000'
'001'
'010'
'011'
'100'
'101'
'110'
'111'
Correspondency between FIFOs, CHANNELs and SLOTs
FIFO#
CHANNEL#
B1_RSL, B1_SSL, B2_RSL, B2_SSL, AUX1_RSL, AUX1_SSL, AUX2_RSL and
AUX2_SSL
CHANNEL after RESET Possible Connections in Simple Mode (SM)
B1-transmit channel (S/T) B1-transmit channel (S/T)
B1-receive channel (S/T)
B2-transmit channel (S/T) B2-transmit channel (S/T)
B2-receive channel (S/T)
D-transmit channel (S/T)
D-receive channel (S/T)
invalid (E is receive only)
E-receive channel (S/T)
(CON_HDLC, bits 7..5)
PCM-transmit timeslot selected by B1_SSL
B1-receive channel (S/T)
PCM-receive timeslot selected by B1_RSL
PCM-transmit timeslot selected by B2_SSL
B1-receive channel (S/T)
PCM-receive timeslot selected by B2_RSL
D-transmit channel (S/T)
PCM-transmit timeslot selected by AUX1_SSL
D-receive channel (S/T)
PCM-receive timeslot selected by AUX1_RSL
PCM-transmit timeslot selected by AUX2_SSL
E-receive channel (S/T)
PCM-receive timeslot selected by AUX2_RSL
Cologne
Chip