IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 80

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
3.19
transmitted or the data stream to be transmitted can be extracted to the
PRBS Generator/Detector for test in this block.
PCCE bit must be set to ‘1’.
TSDn/MTSDA (MTSDB) pins on a per-channel/per-TS basis or on a glo-
bal basis of the corresponding link (the methods are arranged from the
highest to the lowest in priority):
data to be transmitted will be extracted to the PRBS Generator/Detector.
The data to be transmitted can be extracted in unframed mode, in 8-bit-
based mode or in 7-bit-based mode. This selection is made by the PRB-
SMODE[1:0] bits. In unframed mode, all the data stream to be transmit-
ted is extracted and the per-channel/per-TS configuration in the TEST
bit is ignored. In 8-bit-based mode or in 7-bit-based mode, the data will
only be extracted on the channel/timeslot configured by the TEST bit.
Refer to Chapter 3.27.1 PRBS Generator / Detector for details.
pression can be selected to implement to the data of all the channels of
the corresponding link. This function is only supported in T1/J1 mode.
timeslots of the corresponding link will be replaced by the trunk code set
in the DTRK[7:0] bits, the milliwatt pattern defined in Table 36 and
Table 37, or the payload loopback data from the Elastic Store Buffer
(refer to Chapter 3.27.2.2 Payload Loopback). When the GSUBST[2:0]
bits are set to ‘000’, these replacements will be performed on a per-
channel/per-TS basis by setting the SUBST[2:0] bits in the correspond-
ing channel/timeslot.
TSIGn/MTSIGA (MTSIGB) pins (after processed by the signaling trunk
conditioning replacement and/or valid signaling bits selection) can be
inserted into its signaling bit position of the data stream to be transmit-
ted.
setting the SINV, OINV, EINV bits.
data to be transmitted will be replaced by the test pattern generated
from the PRBS Generator/Detector. The data to be transmitted can be
replaced in unframed mode, in 8-bit-based mode or in 7-bit-based
mode. This selection is made by the PRBSMODE[1:0] bits. In unframed
mode, all the data stream to be transmitted is replaced and the per-
channel/per-TS configuration in the TEST bit is ignored. In 8-bit-based
mode or in 7-bit-based mode, the data will only be replaced on the chan-
nel/timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
from the TSIGn/MTSIGA (MTSIGB) pins on a per-channel/per-TS basis
or on a global basis of the corresponding link. The processed signaling
bits will be inserted to the data stream to be transmitted if frame is gen-
erated. The methods are arranged from the highest to the lowest in pri-
ority:
Different test patterns can be inserted in the data stream to be
To enable all the functions in the Transmit Payload Control, the
The following methods can be executed on the data input from the
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
- Configured by the ZCS[2:0] bits, four types of Zero Code Sup-
- Selected by the GSUBST[2:0] bits, the data of all channels/
- Controlled by the SIGINS bit, the signaling bits input from the
- Invert the most significant bit, the even bits and/or the odd bits by
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
The following methods can be executed on the signaling bits input
TRANSMIT PAYLOAD CONTROL
69
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
channels/timeslots of the corresponding link will be replaced by the sig-
naling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is ‘0’, the replacement can be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Table 45: Related Bit / Register In Chapter 3.19
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
ZCS[2:0] (T1/J1 only)
SIGINS (T1/J1 only)
ABXX (T1/J1 only)
PRBSMODE[1:0]
ADDRESS[6:0]
GSUBST[2:0]
- Selected by the ABXX bit, the signaling bits can be valid in the
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
The indirect registers of the Transmit Payload Control are accessed
SUBST[2:0]
GSTRKEN
DTRK[7:0]
PRBSDIR
SIGSNAP
STRKEN
TESTEN
A,B,C,D
PCCE
D[7:0]
BUSY
TEST
OINV
SINV
EINV
RWN
Bit
ID * - Data Trunk Conditioning
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
ID * - Signaling Trunk Condi-
TPLC / RPLC / PRGD Test
TPLC Access Control
TPLC Control Enable
TPLC Access Status
TPLC Configuration
TPLC Access Data
Configuration
tioning Code
Register
Code
T1/J1) / 41~4F & 51~5F
T1/J1) / 20~3F (for E1)
T1/J1) / 00~1F (for E1)
TPLC ID * - 41~58 (for
TPLC ID * - 21~38 (for
TPLC ID * - 01~18 (for
0CC, 1CC, 2CC, 3CC,
4CC, 5CC, 6CC, 7CC
0CB, 1CB, 2CB, 3CB,
0CA, 1CA, 2CA, 3CA,
4CB, 5CB, 6CB, 7CB
4CA, 5CA, 6CA, 7CA
0C7, 1C7, 2C7, 3C7,
0C9, 1C9, 2C9, 3C9,
0C8, 1C8, 2C8, 3C8,
4C7, 5C7, 6C7, 7C7
4C9, 5C9, 6C9, 7C9
4C8, 5C8, 6C8, 7C8
Address (Hex)
March 22, 2004
(for E1)