IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 72

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
on the RSDn and RSIGn pins. The pulse on the RSFSn pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3
to output the data from all eight links. The data of Link 1 to Link 4 is byte-
interleaved output on the multiplexed bus 1, while the data of Link 5 to
Link 8 is byte-interleaved output on the multiplexed bus 2. When the
data from the four links is output on one multiplexed bus, the sequence
of the data is arranged by setting the timeslot offset. The data from dif-
ferent links on one multiplexed bus must be shifted at a different timeslot
offset to avoid data mixing.
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all eight links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-timeslot aligned with the corresponding data on
the MRSDA (MRSDB) pin.
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSDA (MRSDB)
and MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the
DE bit of the eight links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MRSFS is
ahead. The MRSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the eight links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always sam-
pled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
eight links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125 µs, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB)
Functional Description
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
In the Receive Multiplexed mode, two multiplexed buses are used
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Except that in the Receive Master mode, when the OHD bit, the
Receive Multiplexed Mode
Offset
pin.
The
signaling
bits
on
the
RSIGn/
61
MRSIGA(MRSIGB) pin are always per-timeslot aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
different operating modes and the configuration of the offset.
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
MRSIGA(MRSIGB)
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
Table 41: Related Bit / Register In Chapter 3.17
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Note:
* ID means Indirect Register in the Receive Payload Control function block.
ALTIFS (T1/J1 only)
FBITGAP (T1/J1
MAP[1:0] (T1/J1
SMFS (E1 only)
OHD (E1 only)
TSOFF[6:0]
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
BOFF[2:0]
RCOFAE
RSLVCK
RMODE
RCOFAI
RMUX
CMFS
FSINV
EDGE
PCCE
G56K
CMS
only)
GAP
only)
TRI
Bit
FE
DE
Output
Backplane Global Configuration
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
RTSFS Change Indication
RTSFS Interrupt Control
On
RPLC Control Enable
RBIF Frame Pulse
RBIF Operation
RBIF Bit Offset
RBIT TS Offset
RBIF Mode
Register
RSDn/MRSDA(MRSDB)
T1/J1) / 00~1F (for E1)
04BH, 14B, 24B, 34B,
RPLC ID - 01~18 (for
0D1, 1D1, 2D1, 3D1,
04C, 14C, 24C, 34C,
4D1, 5D1, 6D1, 7D1
04A, 14A, 24A, 34A,
44C, 54C, 64C, 74C
44A, 54A, 64A, 74A
44B, 54B, 64B, 74B
047, 147, 247, 347,
046, 146, 246, 346,
048, 148, 248, 348,
049, 149, 249, 349,
447, 547, 647, 747
446, 546, 646, 746
448, 548, 648, 748
449, 549, 649, 749
Address (Hex)
March 22, 2004
010
&
RSIGn/