IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 70

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame output on the RSDn/MRSDA(MRSDB) pin will
delay ‘N’ clock cycles to the framing pulse on the RSFSn/MRSFS pin.
(Here ‘N’ is defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and
the TSOFF[6:0] bits are set, the start of the corresponding frame output
on the RSDn/MRSDA(MRSDB) pin will delay ‘8 x M’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSDA(MRSDB) pin will delay ‘2 x N’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘N’ is defined by the
BOFF[2:0] bits.) When the CMS bit is ‘1’ (i.e., in double clock mode) and
the TSOFF[6:0] bits are set, the start of the corresponding frame output
Functional Description
The bit offset and channel offset are configured when the
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Figure 22. No Offset When FE = 0 & DE = 1 In Receive Path
Figure 23. No Offset When FE = 1 & DE = 0 In Receive Path
FE = 1, DE = 0
FE = 0, DE = 1
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
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on the RSDn/MRSDA(MRSDB) pin will delay ‘16 x M’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
MRSIGA(MRSIGB)
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In Non-multiplexed mode, the channel offset can be configured
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
Output
Bit 2
Bit 2
Bit 2
On
Bit 2
RSDn/MRSDA(MRSDB)
March 22, 2004
&
RSIGn/