IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 79

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer
multiple of 125 µs, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is ‘1’.
3.18.2.3
to transmit the data to all eight links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1, while the data of Link 5 to
Link 8 is byte-interleaved input from the multiplexed bus 2. When the
data on one multiplexed bus is input to four links, the sequence of the
data is arranged by setting the timeslot offset. The data to different links
from one multiplexed bus must be shifted at a different timeslot offset to
avoid data mixing.
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all eight links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-timeslot aligned with the corresponding data on
the MTSDA (MTSDB) pin.
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSDA (MTSDB)
and MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the
DE bit of the eight links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MTSFS is
ahead. The MTSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the eight links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always sam-
pled on its first active edge.
Basic frame, CRC Multi-frame and/or Signaling Multi-frame of the first
link. The indications are selected by the FSTYP bit. The active polarity of
the MTSFS is selected by the FSINV bit. The FSTYP bit and the FSINV
bit of the eight links should be set to the same value. If the pulse on the
MTSFS pin is not an integer multiple of 125 µs, this detection will be
indicated by the TCOFAI bit. If the TCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the TCOFAI bit is ‘1’.
3.18.2.4
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
In the Transmit Clock Slave mode, the TSFSn can indicate the
In the Transmit Multiplexed mode, two multiplexed buses are used
In the Transmit Multiplexed mode, the timing signal on the MTSCK
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the MTSFS can indicate the
Bit offset and timeslot offset are both supported in all the operating
Transmit Multiplexed Mode
Offset
68
MTSDA(MTSDB)
MTSIGA(MTSIGB) pin are always per-timeslot aligned with the data on
the TSDn/MTSDA(MTSDB) pin.
different operating modes and the configuration of the offset.
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
Table 44: Related Bit / Register In Chapter 3.18
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
(T1/J1 only)
(T1/J1 only)
TSOFF[6:0]
BOFF[2:0]
FBITGAP
MAP[1:0]
TCOFAE
TSLVCK
TMODE
TCOFAI
MTSDA
FSTYP
TMUX
FSINV
EDGE
PCCE
G56K
CMS
GAP
Refer to Chapter 3.18.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured
Bit
FE
DE
ID * - Channel Control (for T1/J1) /
Backplane Global Configuration
RTSFS Change Indication
Timeslot Control (for E1)
RTSFS Interrupt Control
pin.
TBIF Operating Mode
TPLC Control Enable
TBIF Option Register
TBIF TS Offset
TBIF Bit Offset
Register
The
signaling
bits
043, 143, 243, 343, 443,
042, 142, 242, 342, 442,
045, 145, 245, 345, 445,
044, 144, 244, 344, 444,
T1/J1) / 00~1F (for E1)
TPLC ID * - 01~18 (for
0CC, 1CC, 2CC, 3CC,
4CC, 5CC, 6CC, 7CC
04C, 14C, 24C, 34C,
04B, 14B, 24B, 34B,
44C, 54C, 64C, 74C
44B, 54B, 64B, 74B
on
Address (Hex)
543, 643, 743
542, 642, 742
545, 645, 745
544, 644, 744
March 22, 2004
010
the
TSIGn/