IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 15

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
2
Note:
* The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘,...’ is followed, this bit is in a per-link control reg-
ister and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.
Pin Description
RSD[1] / MRSDA[1]
RSD[2] / MRSDB[1]
RSD[5] / MRSDA[2]
RSD[6] / MRSDB[2]
RRING[1]
RRING[2]
RRING[3]
RRING[4]
RRING[5]
RRING[6]
RRING[7]
RRING[8]
TRING[1]
TRING[2]
TRING[3]
TRING[4]
TRING[5]
TRING[6]
TRING[7]
TRING[8]
RTIP[1]
RTIP[2]
RTIP[3]
RTIP[4]
RTIP[5]
RTIP[6]
RTIP[7]
RTIP[8]
TTIP[1]
TTIP[2]
TTIP[3]
TTIP[4]
TTIP[5]
TTIP[6]
TTIP[7]
TTIP[8]
RSD[3]
RSD[4]
RSD[7]
RSD[8]
Name
PIN DESCRIPTION
Output
High-Z
Output
Type
Input
Pin No.
N14
G14
H13
M13
N15
H16
R16
C11
F14
L13
D11
A12
E16
K16
T16
A11
F16
L16
J13
J16
M4
M2
D8
D6
B4
D9
D5
C4
A8
A7
A1
A9
A6
A2
P3
R2
R1
P1
N2
L5
RTIP[1:8] / RRING[1:8]: Receive Bipolar Tip/Ring for Link 1 ~ 8
These pins are the differential line receiver inputs.
TTIP[1:8] / TRING[1:8]: Transmit Bipolar Tip/Ring for Link 1 ~ 8
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A
logic high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-023H,... / b4,
E1-023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high impedance state.
Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line Driver for
details).
RSD[1:8]: Receive Side System Data for Link 1 ~ 8
The processed data stream is output on these pins.
In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, determined by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins are
updated on the active edge of the corresponding RSCKn or all eight RSDn pins are updated on the active edge of
RSCK[1].
MRSDA[1:2] / MRSDB[1:2]: Multiplexed Receive Side System Data A / B for Link 1 ~ 8
In Receive Multiplexed mode, the MRSDA[1:2] pins or the MRSDB[1:2] pins are used to output the processed data
stream. Using a byte-interleaved multiplexing scheme, the MRSDA[1]/MRSDB[1] pins output the data from Link 1 to
Link 4, while the MRSDA[2]/MRSDB[2] pins output the data from Link 5 to Link 8. The data on the MRSDA[1:2]/
MRSDB[1:2] pins are updated on the active edge of the MRSCK. The data on MRSDA[1:2] is the same as the data
on MRSDB[1:2]. MRSDB[1:2] are for back-up purpose.
Line and System Interface
4
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
March 22, 2004