IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 67
IDT82P2288
Manufacturer Part Number
IDT82P2288
Description
8 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82P2288.pdf
(384 pages)
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IDT82P2288
3.17.1.1.2
Master mode, the special feature in this mode is that the RSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected position).
‘1’. The RSCKn is also gapped during the channels or the Bit 8 duration
by selecting the G56K & GAP bits in the Receive Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.17.1.2
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the received data
stream (1.544 Mb/s) should be mapped to the same rate as the system
side, that is, to work in T1/J1 mode E1 rate. Three kinds of schemes are
provided by selecting the MAP[1:0] bits:
Channel 15 of Frame N from the device are converted into TS1 to TS15
of Frame N on the system side; Channel 16 to Channel 24 of Frame N
Functional Description
1.544
2.048
Mb/s
Mb/s
1.544
2.048
Mb/s
Mb/s
Besides all the common functions described in the Receive Clock
The RSCKn is gapped during the F-bit if the FBITGAP bit is set to
In the Receive Clock Slave mode, the system data rate can be
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 17): Channel 1 to
filler
F
TS0
filler
Receive Clock Slave Mode
F
CH1
TS0
Receive Clock Master Fractional T1/J1 Mode
the 8th bit
CH1
TS1
TS1
Figure 18. T1/J1 To E1 Format Mapping - One Filler Every Four Channels Mode
CH2
CH2
TS2
TS2
CH3
TS3
Figure 17. T1/J1 To E1 Format Mapping - G.802 Mode
CH14
CH4
TS14 TS15 TS16 TS17 TS18
TS4
filler
CH15
CH5
TS5
TS6
CH16
CH6
filler
TS7
CH7
CH17
56
TS8
filler
from the device are converted into TS17 to TS25 of Frame N on the sys-
tem side. The F-bit of Frame N from the device is converted into the first
bit of TS26 of Frame (N-1) on the system side. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all filled with ‘0’s and
they are meaningless.
Figure 18): One dummy byte is inserted on the system side before 3
bytes of Frame N from the device are converted. This process repeats 8
times and the conversion of Frame N of 1.544 Mb/s data rate to 2.048
Mb/s data rate is completed. However, the F-bit of Frame N of the 1.544
Mb/s data rate is inserted as the 8th bit of Frame N of the 2.048 Mb/s
data rate. The dummy bytes are filled with all ‘0’s and they are meaning-
less.
Channel 1 to Channel 24 of Frame N from the device are converted into
TS1 to TS24 of Frame N on the system side. The F-bit of Frame N from
the device is converted into the 8th bit of Frame N on the system side.
The first 7 bits and TS25 to TS31 on the system side are all filled with
‘0’s and they are meaningless.
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
2. T1/J1 Mode E1 Rate per One Filler Every Four CHs (refer to
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 19):
TS9
CH23
CH22
TS24 TS25
TS28 TS29 TS30 TS31
filler
CH24
CH23
the 1st bit
F
CH24
TS26 TS27~TS31
CH1
filler
F
CH2
CH1
filler
filler
TS0
the 8th bit
CH2
March 22, 2004
TS0
filler
TS1
CH23
TS1
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