IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 20

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
Pin Description
DS / RD / SCLK
VDDDIO
VDDDC
SPIEN
Name
TRST
TMS
TCK
TDO
TDI
High-Z
Power
Power
Type
Input
Input
Input
Input
Input
Input
K12, L12,
J12, K5,
J11, K6,
Pin No.
J9, J10,
F5, G5,
H6, H7,
K8, K9,
H5, J5,
H8, J6,
J7, J8,
L6, L7,
L8, L9,
K10,
K11,
N10
R13
R14
M12
L10,
N11
T14
T15
T13
L11
K7,
DS: Data Strobe (Active Low)
In parallel Motorola mode, this pin is active low.
RD: Read Strobe (Active Low)
In parallel Intel mode, this pin is active low for read operation.
SCLK: Serial Clock
In SPI mode, this pin inputs the timing for the SDO and SDI pins. The signal on the SDO pin is updated on the falling
edge of SCLK, while the signal on the SDI pin is sampled on the rising edge of SCLK.
DS / RD / SCLK is a Schmitt-trigger input.
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up resis-
tor. It must be connected to the RESET pin or ground when JTAG is not used.
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is
clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up
resistor.
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin is a Schmitt-triggered input with an internal
pull-up resistor.
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the
process of data scanning.
VDDDIO: 3.3 V I/O Power Supply
VDDDC: 1.8 V Digital Core Power Supply
JTAG (per IEEE 1149.1)
Power & Ground
9
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
March 22, 2004