IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 357

• Manufacturer Part Number: IDT82P2282
• Description: 2 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2282
6
ACCESS PORT
as described in the IEEE 1149.1 standards.
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
IEEE STD 1149.1 JTAG Test Access Port
The IDT82P2282 supports the digital Boundary Scan Specification
The boundary scan architecture consists of data and instruction
IEEE STD 1149.1 JTAG TEST
TRST
TMS
TCK
TDI
(Test Access Port)
Controller
TAP
DIR (Device Identification Register)
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure 40. JTAG Architecture
Control<6:0>
346
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure - 40 for architecture.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The JTAG boundary scan registers include BSR (Boundary Scan
Output Enable
Select
MUX
October 7, 2003
TDO