IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 321

• Manufacturer Part Number: IDT82P2282
• Description: 2 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2282
E1 TFIFO1 Threshold (0AAH, 1AAH)
E1 TFIFO2 Threshold (0ABH, 1ABH)
E1 TFIFO3 Threshold (0ACH, 1ACH)
FL[1:0]:
0A9H,...) is ‘1’. They define how many times the 7E (Hex) flags is transmitted before the FISU packet transmission.
LL[1:0]:
HL[1:0]:
mitted.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
These bits are valid in SS7 mode when there is no data in the FIFO to be transmitted and the AUTOFISU bit (b5, E1-0A7H,... / 0A8H,... /
= 00: 8 flags
= 01: 16 flags
= 10: 32 flags
= 11: 64 flags
These 2 bits set the lower threshold of the FIFO. If the fill level is below the lower threshold, an interrupt may be generated.
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 96 bytes
These 2 bits set the upper threshold of the FIFO. Once the fill level exceeds the upper threshold, the data stored in the FIFO will start to be trans-
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 128 bytes
7
7
7
Reserved
Reserved
Reserved
6
6
6
R/W
R/W
R/W
FL1
FL1
FL1
5
1
5
1
5
1
R/W
R/W
R/W
FL0
FL0
FL0
4
0
4
0
4
0
310
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
R/W
R/W
R/W
LL1
LL1
LL1
3
0
3
0
3
0
R/W
R/W
R/W
LL0
LL0
LL0
2
0
2
0
2
0
R/W
R/W
R/W
HL1
HL1
HL1
1
0
1
0
1
0
October 7, 2003
HL0
R/W
HL0
R/W
HL0
R/W
0
1
0
1
0
1