IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 313
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IDT82P2282
Manufacturer Part Number
IDT82P2282
Description
2 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82P2282.pdf
(383 pages)
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IDT82P2282
RRST:
/ 096H,... / 097H,...) and the EMP bit (b1, E1-095H,... / 096H,... / 097H,...).
E1 RHDLC1 RFIFO Access Status (095H, 195H)
E1 RHDLC2 RFIFO Access Status (096H, 196H)
E1 RHDLC3 RFIFO Access Status (097H, 197H)
EMP:
PACK:
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
A transition from ‘0’ to ‘1’ on the this bit will reset the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, E1-095H,...
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
= 0: All valid HDLC/SS7 blocks are pushed into the FIFO.
= 1: The FIFO is empty, i.e., all the blocks are read from the FIFO.
The corresponding HDLC Receiver reset will clear this bit.
= 0: The byte read from the FIFO is not an overhead byte.
= 1: The byte read from the FIFO is an overhead byte.
The corresponding HDLC Receiver reset will clear this bit.
7
7
7
6
6
6
5
5
5
Reserved
Reserved
Reserved
4
4
4
302
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
3
3
2
2
2
EMP
EMP
EMP
R
R
R
1
1
1
1
1
1
October 7, 2003
PACK
PACK
PACK
R
R
R
0
0
0
0
0
0
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