IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 135

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IDT82P2282

Manufacturer Part Number
IDT82P2282
Description
2 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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IDT82P2282
T1/J1 Transmit Configuration 3 (025H, 125H)
DONE:
RW:
UI[1:0]:
SAMP[3:0]:
Programming Information
Bit Name
Default
Bit No.
This register is valid when the PULS[3:0] bits (b3~0, T1/J1-023H,...) are set to ‘11xx’.
= 0: Disable the read/write operation to the pulse template RAM.
= 1: Enable the read/write operation to the pulse template RAM.
= 0: Write the data to the pulse template RAM.
= 1: Read the data to the pulse template RAM.
These bits specify one Unit Interval (UI) address.
= 00: UI addressed 0 is specified.
= 01: UI addressed 1 is specified.
= 10: UI addressed 2 is specified.
= 11: UI addressed 3 is specified.
There bits specify one sample address. There are 16 samples in each UI.
Type
DONE
R/W
7
0
SAMP[3:0]
0000
0001
0010
0100
0101
0011
0110
0111
R/W
RW
6
0
Specified Sample Address
R/W
UI1
5
0
0
1
2
3
4
5
6
7
R/W
UI0
4
0
124
SAMP[3:0]
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
1000
1001
1010
1011
1100
1101
1110
1111
SAMP3
R/W
3
0
Specified Sample Address
SAMP2
R/W
2
0
10
11
12
13
14
15
8
9
SAMP1
R/W
1
0
October 7, 2003
SAMP0
R/W
0
0

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