CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 50

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
 2002 CML Microsystems Plc
Tx Section
The Tx section can be powered down by setting bits 5 and 4 in the ClkStopCtrl register, and
disabling the transmit path (bit 3 of TxSetup). Note that the transmit path should not be disabled
until the transmit path active status bit in the Status1 register has been cleared.
The power up time for the Tx section is limited by the filter response time. Thus the analogue
circuitry will be correctly biased to receive data by the time the data emerges from the digital
filters.
Rx Section
The Rx section can be powered down by setting bits 3 and 0 in the ClkStopCtrl register, and
disabling the receive path (bit 3 of RxSetup1).
All of the analogue circuitry within the Rx will power up within 10 s. Thus, the time from power up
to valid data appearing at the RxDat pin will be dominated by the digital filter group delay
(nominally 8 symbol periods).
Voice Codec
The voice codec section powers down automatically when disabled (bit 3 of the CodecSetup2
register set low). The output amplifiers are powered down by setting bits 5 and 4 of the
CodecSetup1 register low.
The voice codec section takes 1 sample (288/MCLK) to power up.
Bias Section
When the Voice codec, Tx, Rx and Aux ADC are powered down, a small amount of current can be
saved by setting bit 5 of the PowerDownCtrl register. This bit powers down the analogue bias
chain. However, this causes the voltage on the BIAS1 pin, which is used as the internal "analogue
ground", to move towards VDD with a 250 s time constant. Up to 2ms should be allowed for this
node to recover before enabling the Aux ADC or Tx, Rx, codec sections.
Serial Interface
A small power saving can be made if it is possible to run with a serial interface clock rate of
MCLK/4. Note that this reduces the Rx output rate to four samples per symbol, although symbol
timing can still be adjusted using bit 6 of the RxSetup1 register and the vernier control in the
RxSetup2 register.
When running with a low serial interface clock rate, it is possible to invoke the serial interface
clock stop mode by setting bit 1 of the ClkStopCtrl register. When this mode is active, all FSB
serial interface activity will stop if there is no activity on any frame sync pin for more than 7 symbol
clock periods.
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CMX981
D/981/1