CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 19

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
5.8
 2002 CML Microsystems Plc
Transmission of Data
The eight points in the DQPSK constellation each have a magnitude of 1 and are spaced at 45
intervals around the unit circle. The default operating mode modulates two bit symbols into the
TETRA constellation by representing each symbol as a phase change, according to the following
mapping, where the left hand bit is considered as the first bit of the symbol and corresponds to bit
0, 2, 4 or 6 of the data word written to the FIFO.
When writing to the FIFO with the symbol modulator active, bit 8 of the data word controls the
format of the word. If this bit is set low, the symbol modulator will encode one symbol per word
written to the FIFO. Therefore, data words are read from the FIFO at 18kHz. If the bit is set high,
the symbol modulator encodes four symbols per word, and data words are read from the FIFO at
4.5kHz.
If the symbol modulator is bypassed, the FIFO word is interpreted as an absolute constellation
position given by the table below.
Bit 9 of each data word (regardless of whether the modulator is bypassed or not) controls the
initiation, ramp up, ramp down and termination of a transmission frame. The user initiates a
transmit frame by enabling bit 3 in the TxSetup register. However, internal transmission of the
data will not occur until a data word is read from the FIFO with the ramp up bit set (bit 9). This
read occurs at the symbol clock. The symbol clock can be automatically adjusted to the next
sample clock by setting bit 7 in the TxSetup register when enabling the transmit path. This
effectively allows transmission to start on the next sample clock. Therefore, there is a variable
delay between enabling the transmit data path and transmission starting. The user may poll the
transmit path enabled bit in the Status1 register to establish when transmission has started. The
ramping feature has a built in delay equal to the latency of the default FIR filter coefficients. This
delay can be varied by use of the RampCtrl register.
To relieve the user of polling overheads when waiting for Tx frame completion, an interrupt can be
set up to occur when the transmit path is disabled.
Bit code
Q
I
Bit 0, 2, 4 or 6
000
1
0
0
1
1
0
0.7071
0.7071
001
Symbol
010
0
1
Bit 1, 3, 5 or 7
19
-0.7071
0.7071
011
1
1
0
0
100
-1
0
-0.7071
-0.7071
101
Phase change
+135
-135
+45
-45
110
-1
0
-0.7071
0.7071
111
CMX981
D/981/1