CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 17

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
 2002 CML Microsystems Plc
Write commands (CmdDat1, CmdDat2 and TxDat pins)
Read commands (CmdDat1 and CmdDat2 pins)
Normal mode
Response to read command (CmdRdDat1, CmdRdDat2 and RxDat pins)
bidirectional
CmdDat1 in
FSB Operation
The three interfaces share a common serial clock pin. The serial clock rate is selectable between
MCLK, MCLK/2 and MCLK/4 in the ConfigCtrl1 register.
Write commands are issued by setting the first bit transmitted high (bit 15). All three ports can
write to any address (except read only locations). Write commands issued on the Tx port will be
executed before Cmd1 port commands, which will be executed before Cmd2 port commands, if
more than one write command is issued simultaneously.
Read commands are issued by setting the first bit transmitted low (bit 15). Read commands
issued by the Tx port are ignored. Read commands issued on the Cmd1 port will be executed
before Cmd2 port commands, if two read commands are issued simultaneously.
The Rx port is used mainly for the output of I and Q received data. When data reception is
enabled, I and Q received data will be output at 8x the symbol rate. If the serial clock rate is set to
MCLK/4, data will be output at 4x the symbol rate. In this mode, alternate samples are discarded.
16-bit data words are output from alternate channels (I channel first). To facilitate channel
identification of the serial data, should initial synchronisation be lost, the CMX981 has an I/Q
channel identification mode, which is controlled by setting bit 5 in the RxSetup1 register. Enabling
this mode causes the LSB of the Q channel to be a logic "1", while the LSB of the I channel is a
logic "0" for seven samples out of eight. The eighth sample is a logic "1" and coincides with the
internal symbol clock.
SCLK
FS
DAT
RDFS
RDDAT
mode
Bit
Bit
Bit
15
15
15
1
0
0
0
14
14
14
10-12 clock cycles
15 14 13 12
13
13
13
12
12
12
Address
Address
Address
Address
Figure 5 FSB Operation
11
11
11
10
10
10
15 14 13 12
3
17
2
9
9
9
1
8
8
8
0
7
7
7
3
6
6
6
2
5
5
5
1
Ignored bits
Write data
Read data
Read data
4
4
4
0
3
3
3
2
2
2
1
1
1
0
0
0
CMX981
D/981/1