CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 18

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
CSN
CCLK
CDATA
RDATA
5.7
 2002 CML Microsystems Plc
C-BUS Operation
When the CBUSEN pin is set high, Cmd port 1 is configured as a C-BUS interface.
Notes:
Data on the CDATA line is clocked into the CMX981 on the rising edge of the CCLK input. The
reply data sent from the CMX981 is valid when the CCLK input is high. The CSN line must be held
low during a data transfer and kept high between transfers. The C-BUS interface is compatible
with most common C serial interfaces and may also be easily implemented with general purpose
Interrupt Function
Two interrupt request (IRQ) pins (N_IRQ1 and N_IRQ2) are provided for asynchronous
communication with an external processor. Some examples of operation that may generate an
interrupt are:
1. An attempt is made by the user to write to the Tx FIFO when it is full.
2. An internal arithmetic overflow has occurred in an FIR filter.
3. The voice codec has just written a new output sample and requires a new input sample.
The IRQ feature may also be used to establish the phasing of the received I and Q channel data
from the Rx serial port should synchronisation be lost for any reason.
In order for these pins to generate interrupts, the user must first program which status register(s)
will cause interrupts on which pin(s). This is done using the IRQCtrl register. Each status register
has an associated mask register, which is used to select which bits of each register causes
interrupt. The cause of an IRQ can be obtained by reading the status registers. All possible
causes of an interrupt are masked on reset. Mask status can be altered by writing to the IRQ
mask register.
C I/O pins controlled by a simple software routine.
1. The CDATA and RDATA lines are never active at the same time. The WR bit determines
2. The CCLK input can be high or low at the start and end of each C-BUS transaction.
3. The gap shown between the address and data bytes is optional. The user may insert gaps
the data direction for each C-BUS transfer - high being a write transaction, low being a
read transaction.
or concatenate the data as required.
Data value unimportant
WR
MSB
6
5
Address byte
High Z state
4
Figure 6 C-BUS Operation
3
2
1
LSB
0
18
MSB
MSB
7
7
6
6
5
5
4
4
Data byte
3
3
Either logic level valid
2
2
1
1
LSB
LSB
0
0
CMX981
D/981/1