CMX981 Consumer Microcircuits Limited, CMX981 Datasheet
CMX981
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CMX981 Summary of contents
Page 1
... RAdio (TETRA) system applications and is also sufficiently flexible for use in other demanding digital radio systems. The CMX981 transmit path comprises all functions required to convert digital ‘symbol’ data into suitably filtered analogue I and Q signals for external up-conversion and transmission. This includes digital control of output amplitudes and offsets and fully programmable digital filters. ...
Page 2
... Advanced Digital Radio Baseband Processor (Continued from front page) The CMX981 receive path accepts differential analogue baseband I/Q signals, samples them and performs digital channel select filtering to simplify host processing and data extraction. Internal digital offset correction and the digital filters are fully programmable. Default coefficients provide the RRC response required for TETRA ...
Page 3
... Note: This product is in development: Changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. Information in this data sheet should not be relied upon for final product design. 2002 CML Microsystems Plc CONTENTS 3 CMX981 Page D/981/1 ...
Page 4
... Advanced Digital Radio Baseband Processor 2. Block Diagram 2002 CML Microsystems Plc Figure 1 Block Diagram 4 CMX981 D/981/1 ...
Page 5
... O/P Transmit "I" channel, positive output O/P Transmit "I" channel, negative output O/P Transmit "Q" channel, positive output O/P Transmit "Q" channel, negative output 5 Description / FSB select when active and a high SSD when active and a high SSD CMX981 D/981/1 ...
Page 6
... Analogue bias level. This pin should be decoupled to V SSTX BI DAC reference level. This pin should normally be connected to V Power Rx analogue positive supply rail. This pin should be decoupled to V Power Tx analogue positive supply rail. This pin should be decoupled CMX981 Description SSTX SSRX SSTX D/981/1 ...
Page 7
... Rx analogue negative supply rail. Ground Tx analogue negative supply rail. Ground Auxiliary analogue negative supply rail. Ground Voice codec analogue negative supply rail. Ground Power amplifier negative supply rail. Ground Primary digital negative supply rail. 7 CMX981 Description SSTX SSAUX SSVC SSPA SSD D/981/1 ...
Page 8
... products may be scaled with MCLK, but care should be taken to ensure that the FIR filter coefficients are designed to compensate for any amplitude and phase distortion due to both on and off-chip filter components. This compensation is included in the default filter coefficients. See section 6.3 for further details. 2002 CML Microsystems Plc 8 CMX981 D/981/1 ...
Page 9
... Figure 2d Recommended External Components - Codec Speaker Outputs CERAMIC RECEIVERS Figure 2e Recommended External Components - Codec Earpiece Output R4 > > 100 F. 2002 CML Microsystems Plc MIC1P MIC1N AUDPP AUDPN (50nF) R5 EAR 9 C4 MIC2P C4 MIC2N DYNAMIC RECEIVERS (8 ) AUDPP AUDPN DYNAMIC RECEIVERS ( EAR CMX981 D/981/1 ...
Page 10
... Figure 2 Recommended External Components To achieve good noise performance, V extraneous in-band signals are very important recommended that the printed circuit board be laid out with a ground plane in the CMX981 area to provide a low impedance connection between the V and the V and V decoupling capacitors also important to achieve a low impedance connection ...
Page 11
... However the user is then responsible for ensuring that user supplied values do not cause arithmetic overflows to occur within an accumulation cycle. Overflow logic within each filter can detect such events and cause interrupts to be generated under user control. 2002 CML Microsystems Plc 11 CMX981 D/981/1 ...
Page 12
... A look up table provides the digitally encoded I and Q values for each phase state. 2002 CML Microsystems Plc where the filter tap length, (n- the nth filter coefficient the data sample supplied to the (n-k) filter n-k samples previously 12 CMX981 the Tx and D/981/1 ...
Page 13
... This filter takes data from the modulator at the symbol rate (18kHz) and interpolates to the sample rate (144kHz). The CMX981 has a mode that allows data to be written directly to this filter at either rate. The second filter has 63 taps and provides the primary Root Raised Cosine (RRC) shaping with a roll-off factor ( ) of 0 ...
Page 14
... CodecData register and written receive data to it. This data must be read and new data written before the next codec sample clock. 5.5.2 Microphone Inputs The analogue input amplifier selects between two differential microphone sources. This amplifier has a selectable 20dB gain and a mute option. 2002 CML Microsystems Plc 14 CMX981 of D/981/1 ...
Page 15
... CodecGain1 register. 2002 CML Microsystems Plc Bandpass ADC DAC Bandpass Figure 3 Voice Codec Block Diagram 15 Decimation Filter Filter SideTone Amp -12.5dB to -27.5dB -1dB Steps Tone Generator Tone Amp 0 to -30dB -2dB Steps Interpolation Filter Filter Register BUS CMX981 D/981/1 ...
Page 16
... Advanced Digital Radio Baseband Processor 5.5.8 Output Drivers The decoded analogue signal is driven off the CMX981 via either a differential speaker driver or a single-ended earpiece driver. The integrated speaker driver is capable of driving 100mW into an 8 load and the integrated earpiece driver is capable of driving 16.5mW into a 32 load. ...
Page 17
... MCLK/4, data will be output at 4x the symbol rate. In this mode, alternate samples are discarded. 16-bit data words are output from alternate channels (I channel first). To facilitate channel identification of the serial data, should initial synchronisation be lost, the CMX981 has an I/Q channel identification mode, which is controlled by setting bit 5 in the RxSetup1 register. Enabling this mode causes the LSB of the Q channel logic " ...
Page 18
... Data on the CDATA line is clocked into the CMX981 on the rising edge of the CCLK input. The reply data sent from the CMX981 is valid when the CCLK input is high. The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with most common C serial interfaces and may also be easily implemented with general purpose C I/O pins controlled by a simple software routine ...
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... CML Microsystems Plc Symbol Bit 001 010 011 0.7071 0 -0.7071 0.7071 1 0.7071 19 Phase change -135 +135 +45 -45 100 101 110 -1 -0.7071 0 0 -0.7071 -1 CMX981 111 0.7071 -0.7071 D/981/1 ...
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... FIFO is not full. In this way, a hardware interlock mechanism is implemented without having to stop the serial clock. Should a frame sync pulse be generated by the CMX981 before the user has data ready to transmit to the FIFO, a read operation should be issued on the Tx port (MSB set low) that will be ignored ...
Page 21
... BS after clock recovery has been performed on the received data. Then, allowing for the fixed Tx path delay, the CMX981 phase can be advanced or retarded so that it is within the specified error limit. The internal symbol clock phase is normally output on the SymClock pin, but can also be output on the N_IRQ1 and N_IRQ2 pins if required by unmasking the symbol clock enable interrupt in the Mask2 register ...
Page 22
... Transmit I channel phase register Transmit I channel gain register Transmit I channel offset register Transmit Q channel phase register Transmit Q channel gain register Transmit Q channel offset register Transmit ramp up increment register Transmit ramp down decrement register 22 CMX981 Read/Write Read/Write Read/Write Read/Write Write only Read/Write Read/Write Read only ...
Page 23
... Voice codec tone frequency register Voice codec transmit/receive data register Direct Write Data Registers Transmit I channel direct write data register Transmit Q channel direct write data register On reset, all register bits are set low. 23 CMX981 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write ...
Page 24
... Disable read port read port 1 2 Bit 3 Signal 0 Symbol Clock (18kHz) 1 Sample Clock (144kHz) 0 Codec Sample Clock (8kHz) 1 Reserved Increment Increment Enable Aux RAM coefficient Aux RAM pointer on RAM on access read read CMX981 0 Disable rx port 0 Enable coefficient RAM access. D/981/1 ...
Page 25
... N_IRQ2 N_IRQ2 Transmit Set-up Register Enable Bypass direct symbol write modulator rate access Sample clock Status3 to Status2 to to N_IRQ1 N_IRQ1 N_IRQ1 Enable Select Enable transmit ramping ramping data path mode CMX981 0 Status1 to N_IRQ1 0 Reset Tx filter coefficients D/981/1 ...
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... Symbol 2 Symbol 1 Not Not IQ Constellation point Used Used Enable Enable Enable receive Rx port Rx port path for read 2 for read When set low, even numbered CMX981 0 0 Reset Rx filter coefficients D/981/1 ...
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... I channel decimation filter sample delay FIFO FIFO FIFO nearly nearly full empty empty Unmask Unmask Unmask FIFO FIFO FIFO nearly nearly full empty empty CMX981 0 0 FIFO IRQ active 0 Not used. Set low. D/981/1 ...
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... Transmit Transmit Symbol 63-tap 79-tap clock filter filter enable overflow overflow Unmask Unmask Unmask transmit transmit symbol 63-tap 79-tap clock filter filter enable overflow overflow CMX981 0 Transmit IRQ active 0 Not used. Set this bit low. D/981/1 ...
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... Rx low- Rx RRC Even pass filter filter sample overflow overflow` phase Unmask Unmask Unmask Rx low- Rx RRC even pass filter filter sample overflow overflow phase CMX981 0 Rx IRQ active. 0 Not used. Set this bit low. D/981/1 ...
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... Not Used. Set this Phase change bit low Phase change Set serial Stop Aux Stop interface RAM receive auto clock DAC port clock stop clock mode CMX981 0 0 Set Rx auto clock stop mode D/981/1 ...
Page 31
... Power Power Power down Aux down Aux down Aux DAC4 DAC3 DAC2 Enable Enable Enable receive transmit analogue data path data path loop back access access CMX981 0 Power down Aux DAC1 0 Enable digital loop back D/981/1 ...
Page 32
... Auxiliary ADC Control Register Enable Enable ADC 6 ADC Enable Scan auto cycle direction scan Rate of change MCLK/512 MCLK/256 MCLK/128 MCLK/64 MCLK/32 MCLK/16 MCLK/8 MCLK Enable Enable Enable ADC 4 ADC 3 ADC 2 CMX981 0 Enable RAM DAC 0 Enable ADC 1 D/981/1 ...
Page 33
... Not used. Not used. Not used. Set this bit Set this bit Set this bit low. low. low. Transmit Path Ramping Delay Register Number of samples delay time Select Enable Start conversion continuous conversion rate conversion CMX981 0 0 D/981/1 ...
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... Transmit RRC Filter Coefficient [15: Receive Low Pass Filter Coefficient [7: Transmit Low Pass Filter Coefficient [15: Transmit RRC Filter Coefficient [11: Transmit 79-tap Filter Coefficient [11: CMX981 D/981/1 ...
Page 35
... G val Not Used. Not Used. Not Used. Undefined Undefined Undefined on read. on read. on read Transmit I channel gain [11:8] is the signal output, is the value in the register. CMX981 Transmit I channel phase [ D/981/1 ...
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... Undefined on read. on read. on read Transmit I channel offset [11:8] is the signal output. is the value in the register Not Used. Not Used. Not Used. Undefined Undefined Undefined on read. on read. on read. CMX981 Transmit Q channel phase [8] D/981/1 ...
Page 37
... D is the signal output. in off out D is the signal input, and the value in the register. off Transmit Q channel gain [11: Transmit Q channel offset [11:8] CMX981 D/981/1 ...
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... Not Used. Not Used. Not Used. Undefined Undefined Undefined on read. on read. on read Not Used. Not Used. Not Used. Undefined Undefined Undefined on read. on read. on read. CMX981 Transmit ramp up increment [ Transmit ramp down decrement [8] D/981/1 ...
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... Receive Q channel gain [7: Receive Q channel gain [15: where the signal output, in val out D is the signal input, and the value in the register. val CMX981 D/981/1 ...
Page 40
... N is the value in the register. off Receive Data Access Points Receive I Channel Data Access Point Receive Q Channel Data Access Point Receive channel data [7: Receive channel data [15: CMX981 D/981/1 ...
Page 41
... Not used. Not used. Bit value Bit value Bit value undefined undefined undefined ADC Data [9: Transmit channel data [13: Not used. Not used. Bit value Bit value ADC Data [1:0] undefined undefined 3 2 CMX981 D/981/1 ...
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... Not used. Not used. Set this Set this RAM data [1:0] bit low. bit low Not used. Not used. Set this bit Set this bit DAC Data [1:0] low. low CMX981 D/981/1 ...
Page 43
... Set this Set this high pass bit low. bit low. filtering Disable Disable Mute output input input 6dB gain 20dB gain signal Enable Enable Enable voice sidetone ring tone codec CMX981 0 Select mic input 0 Enable transmit signal D/981/1 ...
Page 44
... Bit 2 Bit 1 Bit 0 Gain (dB CMX981 0 Output Gain (dB -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 0 -12.5 -13.5 -14.5 -15.5 -16.5 -17.5 -18.5 -19.5 -20.5 -21.5 -22.5 -23.5 -24.5 -25.5 -26.5 -27.5 D/981/1 ...
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... Transmit Path Direct Write Data Register (Write only) Transmit Path Direct Write Data Register (I) Transmit Path Direct Write Data Register ( Direct Write Data [11: Tone Frequency [12: Codec Data [13: CMX981 D/981/1 ...
Page 46
... The basic algorithm is to take the required frequency domain response, apply an inverse Fourier transform and use a windowing function to reduce the impulse response to the desired length. The impulse response is then identical to the required FIR coefficients. In the case of the CMX981, both transmit and receive filters are configured as two cascaded filters. When developing ...
Page 47
... Both approaches are essentially equivalent. 2002 CML Microsystems Plc 4608 2304 1536 0.1 0.4 0.9 47 CMX981 1152 1024 922 1.6 2.1 2.6 D/981/1 ...
Page 48
... CML Microsystems Plc 4608 2304 1536 0.03 0.13 0.29 48 CMX981 1152 920 0.52 0.77 MCLK = 8.912MHz 0 -0.00112409 -0.00449636 -0.00899271 -0.0134891 -0.0191095 -0.0224818 1.14994 -0.0224818 -0.0191095 -0.0134891 -0.00899271 -0.00449636 -0.00112409 0 D/981/1 ...
Page 49
... Guidelines for use of Powersave Modes The CMX981 contains a number of powersave modes. In order to maximise flexibility for architectures and modes of operation, several register bits are available which control different parts of the device. Operation of the various control bits is described in the appropriate sections. ...
Page 50
... When running with a low serial interface clock rate possible to invoke the serial interface clock stop mode by setting bit 1 of the ClkStopCtrl register. When this mode is active, all FSB serial interface activity will stop if there is no activity on any frame sync pin for more than 7 symbol clock periods. 2002 CML Microsystems Plc 50 CMX981 D/981/1 ...
Page 51
... DDD , and V SSVC SSPA SSD Notes 51 Min. Max. Units -0.3 4.5 V -0.3 3.5 V -0.3 3.5 V -0.3 3.5 V -0.3 3.5 V -0.3 3.5 V -0.3 3 0.3 V DDIO - - 0 Min. Max. Units 1275 mW 15 mW/°C -55 +125 °C -40 +85 °C Min. Max. Units 2.25 3.6 V 2.25 2.75 V 2.25 2.75 V 2.25 2.75 V 2.25 2.75 V 2.25 2.75 V 2.25 2.75 V -40 +85 °C 0.5 12.5 MHz CMX981 D/981/1 ...
Page 52
... MCLK frequency. 2002 CML Microsystems Plc = CC2 SS2 CC3 SSB Notes DD1 SSA DDPA SSPA Min. Typ. Max. 6.0 10.0 5.0 8.0 9.0 14.0 9.0 14.0 - 50.0 10.0 16.0 12.0 19.0 9.0 14.0 17.0 26.0 17.0 27.0 2.0 3.0 1.0 2.0 18.0 29.0 30.0 30.0 10.0 CMX981 = 2.25V to Units µ D/981/1 ...
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... CML Microsystems Plc Notes Min. Typ. MCLK/256 2 /4 DQPSK MCLK/64 MCLK 65.0 70.0 10.0 2 1.9 2.0 3 -70.0 -78.0 -80.0 -88.0 -90.0 -92.0 0.35 -0.1 0.0 -2.9 -3.0 -6.6 -6.8 -30.0 4 -72.0 -80.0 -82.0 -90.0 -93.0 -95.0 -104 53 CMX981 Max. Units bps Hz Hz Bits LSB 2 LSB 20.0 dB 0.25 Degrees 0.5 20.0 Symbols 2.1 V -68.0 dBc -76.0 dBc -78.0 dBc -86.0 dBc -88.0 dBc -90.0 dBc dB 0.3 +0.1 dB -3 -70 ...
Page 54
... This multiplication is applied to the signals from the FIR filters. 8. Offset adjustment for each channel is available by loading a 12-bit word into the transmit offset register via the serial interface. 2002 CML Microsystems Plc Notes Min. Typ. -55.0 -60.0 5 0.045 54 CMX981 Max. Units -53.0 dBc -57.0 dBc 0.070 D/981/1 ...
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... CML Microsystems Plc Notes ) SS2 55 Min. Typ. Max. 100 1 1.7 2 90.0 95.0 2 85.0 90.0 3 200 MCLK/4 16 MCLK/4 MCLK/64 MCLK/64 MCLK/128 10 -15.0 5 -110 0.35 -0.2 0 +0.2 -2.9 -3.0 -3.1 -6.5 -6.9 -7.3 -30.0 -70.0 -85.0 CMX981 Units 1.9 V pk- pk-pk Hz Bits LSB 1 LSB 20.0 dB 0.1 Degrees 0.5 17 Symbols D/981/1 ...
Page 56
... These anti-alias filter requirements can be supplied by IF channel filtering, baseband filtering or a combination of both recommended that in order to maximise the performance obtained from the CMX981 for TETRA applications, at least 10dB and 25dB attenuation be provided at MCLK/70 and MCLK/4 respectively, prior to an external AGC function ...
Page 57
... Notes 80/MCLK 5 MCLK/ where A-D clock frequency is programmable to A-D clock frequency Minimum MCLK/16 80/MCLK 57 Min. Typ. Max. 10 10.0 250 4 1 10.0 4.0 5.0 5.0 10 MCLK/84 160/MCLK MCLK/8 5.0 1.0 Maximum MCLK/8 160/MCLK CMX981 Units Bits s Bits Bits rms Bits Hz s Bits Bits D/981/1 ...
Page 58
... Voice Codec Notes 1.02kHz. 2. Relative to gain at 1.02kHz. 2002 CML Microsystems Plc Notes Min. Typ. MCLK/1152 14 0 0.488 -30.0 2.0 -30.0 2.0 15.0 20 TBD 20 100 20 2.0 0 1.5 300 1 0.1 2 -0.25 2 40.0 58 CMX981 Max. Units Hz Bits 3999 -40 0 550 k 80 ...
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... CML Microsystems Plc Marker Min. Typ cslh t 10 cshl t 35 sis t 35 sis t sih t sih t sop t sop t -5 soh t -5 soh t sop t -7 soh t sop t -7 soh 59 CMX981 Max. Units D/981/1 ...
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... Advanced Digital Radio Baseband Processor 2002 CML Microsystems Plc Figure 7a Basic Serial Port Signals 60 CMX981 D/981/1 ...
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... Advanced Digital Radio Baseband Processor 2002 CML Microsystems Plc Figure 7b Command Write operation 61 CMX981 D/981/1 ...
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... Advanced Digital Radio Baseband Processor 2002 CML Microsystems Plc Figure 7c Bi-dir Command Read Operation 62 CMX981 D/981/1 ...
Page 63
... Advanced Digital Radio Baseband Processor Figure 7d Non bi-dir Command Read Operation 2002 CML Microsystems Plc 63 CMX981 D/981/1 ...
Page 64
... Advanced Digital Radio Baseband Processor Figure 7e Rx Data Serial Port Read Operation 2002 CML Microsystems Plc 64 CMX981 D/981/1 ...
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... CML Microsystems Plc Marker Min. Typ. t 1/MCLK CSE t 1/MCLK CSH t 0.0 LOZ t HIZ t 10/MCLK CSOFF t 2/MCLK NXT t 2/MCLK CK t 1/MCLK CH t 1/MCLK CDS t 25 CDH t 50 RDS t 0 RDH 65 CMX981 Max. Units 10/MCLK D/981/1 ...
Page 66
... Advanced Digital Radio Baseband Processor 7.2 Packaging Figure 8 L9 Mechanical Outline: Order as part no. CMX981L9 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied ...