ST72325R6-AUTO STMicroelectronics, ST72325R6-AUTO Datasheet - Page 57

• Manufacturer Part Number: ST72325R6-AUTO
• Description: 8-bit Mcu For Automotive With 16 To 60 Kbyte Flash, Adc, Css, 5 Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

ST72325xxx-Auto
6.6.6
System Integrity (SI) Control/Status register (SICSR)
Table 13.
SICSR
Bit
7
6
5
4
3
2
1
AVDS
RW
7
LVDRF
CSSIE
AVDIE
CSSD
Name
AVDS
AVDF
-
SICSR description
AVDIE
Voltage Detection selection
Voltage Detector interrupt enable
Voltage Detector flag
LVD reset flag
Reserved, must be kept cleared.
Clock security system interrupt enable
Clock security system detection
RW
6
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
0: Voltage detection on V
1: Voltage detection on EVD pin
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 16
details.
0: V
1: V
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See
source flags
LVDRF bit value is undefined.
This bit enables the interrupt when a disturbance is detected by the Clock Security
System (CSSD bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.
This bit indicates that the safe oscillator of the Clock Security System block has
been selected by hardware due to a disturbance on the main clock signal (f
is set by hardware and cleared by reading the SICSR register when the original
oscillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the CSSD bit value is forced to 0.
DD
DD
or V
or V
AVDF
and to
RW
EVD
EVD
5
for more details. When the LVD is disabled by OPTION BYTE, the
over V
under V
Monitoring the VDD main supply on page 53
LVDRF
IT+(AVD)
RW
IT-(AVD)
4
DD
supply
threshold
threshold
Function
3
Supply, reset and clock management
Reserved
2
-
Reset value:
for additional
1
000x 000x (00h)
Table 14: Reset
WDGRF
OSC
RW
0
57/250
). It