ST72325R6-AUTO STMicroelectronics, ST72325R6-AUTO Datasheet - Page 55

• Manufacturer Part Number: ST72325R6-AUTO
• Description: 8-bit Mcu For Automotive With 16 To 60 Kbyte Flash, Adc, Css, 5 Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

ST72325xxx-Auto
Figure 17. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
6.6.3
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
V
V
IT+(EVD)
IT-(EVD)
Clock security system (CSS)
The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and
overfrequencies occurring on the main clock source (f
clock detection control with an internal safe oscillator (f
Clock filter control
The PLL has an integrated glitch filtering capability making it possible to protect the internal
clock from overfrequencies created by individual spikes. This feature is available only when
the PLL is enabled. If glitches occur on f
the CSS filters these automatically, so the internal CPU frequency (f
delivering a glitch-free signal
Clock detection control
If the clock signal disappears (due to a broken or disconnected resonator...), the safe
oscillator delivers a low frequency clock signal (f
some rescue operations.
Automatically, the ST7 clock source switches back from the safe oscillator (f
main clock source (f
When the internal clock (f
software is notified by hardware setting the CSSD bit in the SICSR register. An interrupt can
be generated if the CSSIE bit has been previously set. These two bits are described in the
SICSR register description.
V
EVD
0
OSC
) recovers.
INTERRUPT PROCESS
CPU
V
hyst
(see Figure
) is driven by the safe oscillator (f
1
OSC
18).
(for example, due to loose connection or noise),
SFOSC
Supply, reset and clock management
OSC
) which allows the ST7 to perform
SFOSC
). It is based on a clock filter and a
).
SFOSC
CPU
), the application
) continues
INTERRUPT PROCESS
SFOSC
0
) if the
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