A43L2616-PH Series AMIC Technology, Corp., A43L2616-PH Series Datasheet - Page 8

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A43L2616-PH Series

Manufacturer Part Number
A43L2616-PH Series
Description
1M x 16 Bit x 4 Banks Synchronous DRAM
Manufacturer
AMIC Technology, Corp.
Datasheet
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
(May, 2002, Version 0.0)
Symbol
t
t
t
t
t
t
t
t
t
RAS(max)
t
RRD(min)
RCD(min)
RAS(min)
CDL(min)
RDL(min)
BDL(min)
CCD(min)
RP(min)
RC(min)
2. Minimum delay is required to complete write.
and then rounding off to the next higher integer.
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in new col. Address delay
Last data in row precharge
Last data in to burst stop
Col. Address to col. Address delay
RAS to
CAS
delay
Parameter
CAS Latency
8
3
12
18
18
42
60
12
-6
6
6
6
Version
100
A43L2616-PH Series
AMIC Technology, Inc.
14
20
20
45
63
14
-7
7
7
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
1
1
1
1
1
2
2
2

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