A43L0616A AMIC Technology, Corp., A43L0616A Datasheet

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A43L0616A

Manufacturer Part Number
A43L0616A
Description
512K x 16 Bit x 2 Banks Synchronous DRAM
Manufacturer
AMIC Technology, Corp.
Datasheet

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Document Title
Revision History
(May, 2001, Version 1.0)
512K X 16 Bit X 2 Banks Synchronous DRAM
Rev. No.
0.0
0.1
0.2
1.0
History
Initial issue
Add input/output capacitance specification
Add Cl2 spec for (-5, -5.5, -6)
Modify MRS Set Cycle Waveform error
Add -U for industrial operating temperature range
Final spec. release
Some AC parameter unit update
512K X 16 Bit X 2 Banks Synchronous DRAM
Issue Date
December 4, 2000
February 13, 2001
April 11, 2001
May 29, 2001
AMIC Technology, Inc.
A43L0616A
Remark
Preliminary
Final

Related parts for A43L0616A

A43L0616A Summary of contents

Page 1

... Modify MRS Set Cycle Waveform error 0.2 Add -U for industrial operating temperature range 1.0 Final spec. release Some AC parameter unit update (May, 2001, Version 1.0) 512K X 16 Bit X 2 Banks Synchronous DRAM Issue Date December 4, 2000 February 13, 2001 April 11, 2001 May 29, 2001 A43L0616A Remark Preliminary Final AMIC Technology, Inc. ...

Page 2

... All inputs are sampled at the positive going edge of the system clock General Description The A43L0616A is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock ...

Page 3

... CLK ADD LRAS LRAS LCBR CLK (May, 2001, Version 1.0) Data Input Register 512K X 16 512K X 16 Column Decoder Latency & Burst Length Programming Register LCAS LWE Timing Register CKE CS RAS CAS 2 A43L0616A LDQM LWCBR L(U)DQM WE AMIC Technology, Inc. LWE LDQM DQi ...

Page 4

... Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +3.3V 0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 3 A43L0616A AMIC Technology, Inc. ...

Page 5

... VDD 4 Min Typ CAS , , , 2 = 0º +70º -40º +85º Max Unit 3.6 V VDD See Figure 1 AMIC Technology, Inc. A43L0616A Max Unit Note Note -2mA 2mA OL Note 2 Note 3 ...

Page 6

... IL CC CKE V (min (min (min), CLK V (max 0mA, Page Burst (min) CCD CCD t (min 0.2V 5 A43L0616A Value 0.1 + 0.01 0.1 + 0.01 Speed CAS Latency -5 230 210 190 160 15ns 15ns 250 230 210 ...

Page 7

... OH V (DC) = 0.4V 2mA OL OL 30pF -5 -5.5 CAS Latency Min Max Min 3 5 5.5 1000 4 A43L0616A V =1. =50 OUTPUT O 30pF (Fig Output Load Circuit -6 -7 Max Min Max Min Max 6 7 1000 1000 1000 5 5 2.5 2.5 2.5 2.5 ...

Page 8

... CAS Latency Min Max Min Max 5 5.5 - 5.5 *All AC parameters are measured from half to half. 7 A43L0616A -6 -7 Min Max Min Max 2 2 AMIC Technology, Inc. Unit Note ...

Page 9

... In case of row precharge interrupt, auto precharge and read burst stop. (May, 2001, Version 1.0) CAS Version Latency -5 -5 100 55 60 A43L0616A Unit Note - CLK 2 ...

Page 10

... Valid Don’t Care Logic High Logic Low) 9 A43L0616A DQM BA A10 A9~A0 Notes WE / CODE Row Addr. L Column Addr Column ...

Page 11

... Latency Reserved Reserved Reserved Reserved Reserved 10 A43L0616A Burst Length Burst Length Type BT=0 Sequential Interleave Reserved ...

Page 12

... A43L0616A Interleave Interleave ...

Page 13

... And the write burst length is programmed using A9. A7~A8, A10/AP and BA must be set to low for normal SDRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies. 12 A43L0616A CAS WE (The SDRAM should be in active mode with , WE ...

Page 14

... Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state. 13 A43L0616A CS , ” after the last data input to be written into the RDL during read operation and inhibits ...

Page 15

... If the system with high on CKE uses burst auto refresh during normal operation CAS recommended to used burst 2048 auto refresh cycles immediately after exiting self refresh. 14 A43L0616A (min)”. The minimum number RAS , and CKE with high on CAS ” ...

Page 16

... DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. 2. DQM masks both data-in and data-out. (May, 2001, Version 1.0) 2) Clock Suspended During Read (BL= Read Mask (BL= Hi-Z Hi Hi-Z Hi A43L0616A Masked by CKE Suspended Dout Masked by CKE Hi Hi DQM to Data-out Mask = 2 Hi-Z ...

Page 17

... Last data in to new column address delay. (= 1CLK). CDL (May, 2001, Version 1.0) Note 1 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 DQ(CL2) DQ(CL3) access; read, write and block write. CAS 16 A43L0616A 3) Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 QB1 DA0 QB0 t CDL Note3 AMIC Technology, Inc ...

Page 18

... To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. (May, 2001, Version Note Hi Hi Note 2 17 A43L0616A AMIC Technology, Inc. ...

Page 19

... Version 1.0) Note 2 PRE Note Masked by DQM PRE RDL PRE Note 1 Auto Precharge Starts Note 1 Auto Precharge Starts interrupt of the same/another bank is illegal. CAS 18 A43L0616A from this point. RP AMIC Technology, Inc. ...

Page 20

... Version 1.0) 2) Write Burst Stop (BL=8) PRE D2 D3 Note 1 t RDL 4) Read Burst Stop (BL=4) PRE Note DQ(CL2 DQ(CL3) MRS ACT t 1CLK RP 19 A43L0616A CLK CMD WR STOP (note 2) BDL CLK CMD RD STOP AMIC Technology, Inc. Note ...

Page 21

... Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended. (May, 2001, Version 1.0) 2) Power Down (=Precharge Power Down) Exit t SS Internal CLK A43L0616A CLK CKE t SS Note 2 NOP ACT CMD Note 5 CMD CMD t RC AMIC Technology, Inc. ...

Page 22

... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 21 A43L0616A interrupt can not be issued. CAS AMIC Technology, Inc. ...

Page 23

... A10/AP WE DQM High level is necessary High-Z DQ Precharge Auto Refresh (All Banks) (May, 2001, Version 1. Auto Refresh 22 A43L0616A KEY KEY KEY Mode Regiser Set AMIC Technology, Inc Row Active (A-Bank) : Don't care ...

Page 24

... *Note 2,3 *Note 2 *Note 3 *Note SAC SLZ SHZ Read Write 23 A43L0616A *Note 4 *Note *Note Row Active Precharge AMIC Technology, Inc Don't care ...

Page 25

... Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. BA Precharge 0 Bank A 1 Bank B X Both Bank 24 A43L0616A AMIC Technology, Inc. ...

Page 26

... OH Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD SAC 25 A43L0616A Cb0 Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write Precharge (A-Bank) (A-Bank) AMIC Technology, Inc ...

Page 27

... High Cb0 Cc0 *Note 2 *Note1 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Dc0 Write Read (A-Bank) (A-Bank) before Row precharge, will be written. RDL 26 A43L0616A *Note 2 Cd0 t RDL t CDL *Note3 Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 Write Precharge ...

Page 28

... QAa0 QAa1 QAa2 QAa3 QBb0 Read (A-Bank) (B-Bank) WE RAS CAS , and are high at the clock high going edge. 27 A43L0616A CAc CBd CAe QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 ...

Page 29

... To interrupt burst write by Row precharge, both the write and precharge banks must be the same. (May, 2001, Version 1. High RBb CBb RBb DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 t CDL Write (B-Bank) 28 A43L0616A *Note 2 CAc CBd DBd0 DBd1 t RDL *Note 1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) : Don't care AMIC Technology, Inc ...

Page 30

... High RBb RBb QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Precharge (A-Bank) (B-Bank) Row Active (B-Bank) 29 A43L0616A CBb RAc CAc RAc t CDL *Note 1 DBb0 DBb1 DBb2 DBb3 QAc0 DBb0 DBb1 DBb2 DBb3 Write Read (A-Bank) ...

Page 31

... High QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Auto Precharge Start Point (A-Bank) 30 A43L0616A CBb DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Auto Precharge Write with Auto Precharge Start Point (B-Bank) (B-Bank) : Don't care AMIC Technology, Inc ...

Page 32

... Qa0 Qa1 Qb0 Qb1 Read without Precharge Auto Precharge (B-Bank) (B-Bank) Auto Precharge Strart Point (A-Bank) *Note 1 after A Bank auto precharge starts A43L0616A Qb3 Qb2 Qb3 Row Active (A-Bank) Auto Precharge : Don't care AMIC Technology, Inc. ...

Page 33

... Rb Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 * Note 1 Read with Auto Precharge Auto Precharge Start Point (A-Bank) (B-Bank) Row Active (B-Bank) 32 A43L0616A Qb0 Qb1 Qb2 Qb3 Qb0 Qb1 Db2 Db3 Auto Precharge Start Point (B-Bank) AMIC Technology, Inc. ...

Page 34

... Note 2 1 QAa0 QAa1 QAa2 QAa3 QAa4 2 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank) RAS interrupt. 33 A43L0616A QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Precharge (A-Bank) : Don't care AMIC Technology, Inc. ...

Page 35

... Burst stop is valid only at every burst length. (May, 2001, Version 1. High CAb * Note 1 t BDL * Note 2 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 Write Burst Stop (A-Bank) 34 A43L0616A RDL * Note 3 DAb4 DAb5 Precharge (A-Bank) : Don't care AMIC Technology, Inc. 19 ...

Page 36

... High RBb CAb RAc RBb RAc QAb0 QAb1 QAb0 QAb1 Row Active (A-Bank) Read with Auto Precharge (A-Bank) 35 A43L0616A Note 2 CBc CAd DBc0 QAd0 QAd1 DBc0 QAd0 Read (A-Bank) Write with Auto Precharge (B-Bank) AMIC Technology, Inc. ...

Page 37

... Clock Row Active Read Suspension * Note : DQM needed to prevent bus contention. (May, 2001, Version 1. Qa1 Qa2 Qa3 t SHZ Read 36 A43L0616A Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write Read DQM DQM Clock Write Suspension : Don't care AMIC Technology, Inc ...

Page 38

... Version 1. Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command A43L0616A Qa0 Qa1 Qa2 Read Precharge AMIC Technology, Inc Don't care ...

Page 39

... If the system uses burst refresh. (May, 2001, Version 1. Note 4 * Note 3 Hi-Z Self Refresh Exit 38 A43L0616A min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Inc ...

Page 40

... Minimum 2 clock cycles should be met before new 3. Please refer to Mode Register Set table. (May, 2001, Version 1.0) Auto Refresh Cycle Auto Refresh WE activation at the same clock cycle with address key will set internal RAS activation. 39 A43L0616A High t RC Hi-Z New Command AMIC Technology, Inc. ...

Page 41

... NOP(Continue Burst to End Precharge NOP(Continue Burst to End Precharge ILLEGAL H BA CA,A10/AP ILLEGAL L BA CA,A10/AP ILLEGAL X BA RA, PA ILLEGAL ILLEGAL 40 A43L0616A Action Row Active) Row Active) Row Active AMIC Technology, Inc. Note ...

Page 42

... X X ILLEGAL NOP Idle after NOP Idle after ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address 41 A43L0616A Action Note RCD RCD Auto Precharge PA = Precharge All AMIC Technology, Inc ...

Page 43

... Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 42 A43L0616A Action Note RC RC (min) has to be elapse after CKE’s low RC AMIC Technology, Inc ...

Page 44

... Ordering Information Part No. Cycle Time (ns) A43L0616AV-5 5 A43L0616AV-5.5 5.5 A43L0616AV-6 6 A43L0616AV-7 7 A43L0616AV-7U 7 Note for industrial operating temperature range (May, 2001, Version 1.0) Clock Frequency (MHz) Access Time 200 @ 4 143 @ 5 183 @ 5 143 @ 5 166 @ 5 125 @ ...

Page 45

... A43L0616A unit: inches/mm Detail "A" R0.15 REF. R0.15 REF Detail "A" Nom Max - 1. 1.016 1.05 - 0.45 - 0.21 20.955 21.055 11.76 11.96 10.16 10.26 0.800 - 0.50 0.60 - 5° AMIC Technology, Inc. ...

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