A43L2616-PH Series AMIC Technology, Corp., A43L2616-PH Series Datasheet - Page 35

• Manufacturer Part Number: A43L2616-PH Series
• Description: 1M x 16 Bit x 4 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

BS0, BS1
CLOCK
A10/AP
ADDR
Self Refresh Entry & Exit Cycle
(May, 2002, Version 0.0)
RAS
CAS
CKE
DQM
CS
DQ
WE
0
* Note 7
* Note : TO ENTER SELF REFRESH MODE
Self Refresh Entry
t
1
SS
* Note 1
TO EXIT SELF REFRESH MODE
1.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
4. System clock restart and be stable before returning CKE high.
5.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
2
If the system uses burst refresh.
CS , RAS & CAS with CKE should be low at the same clock cycle.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
CS starts from high.
* Note 2
Hi-Z
3
4
5
6
* Note 3
7
8
9
35
Hi-Z
10
* Note 4
Self Refresh Exit
11
* Note 5
t
12
SS
13
min.
t
RC
14
A43L2616-PH Series
* Note 6
AMIC Technology, Inc.
15
Auto Refresh
* Note 7
16
17
18
: Don't care
19