A43L2616-PH Series AMIC Technology, Corp., A43L2616-PH Series Datasheet - Page 3

• Manufacturer Part Number: A43L2616-PH Series
• Description: 1M x 16 Bit x 4 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Pin Descriptions
(May, 2002, Version 0.0)
CLK
CKE
A0~A11
BS0, BS1
L(U)DQM
DQ
VDD/VSS
VDDQ/VSSQ
NC/RFU
RAS
CS
CAS
WE
Symbol
0-15
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
Name
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V 0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
3
Description
A43L2616-PH Series
AMIC Technology, Inc.