A43E06161 AMIC Technology, Corp., A43E06161 Datasheet
A43E06161
Related parts for A43E06161
A43E06161 Summary of contents
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... Rev. No. History 0.0 Initial issue 0.1 Modify t from 3ns to 2ns SS Modify t from 1.5ns to 1ns SH Modify I from 0.5mA to 200μA CC6 PRELIMINARY (July, 2005, Version 0.1) 512K X 16 Bit X 2 Banks Synchronous DRAM A43E06161 Issue Date Remark May 3, 2005 Preliminary July 31, 2005 AMIC Technology, Corp. ...
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... Deep Power Down Mode Clock Frequency: 105MHz @ CL=3 (-95) 133MHz @ CL=3 (-75) General Description The A43E06161 is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on ...
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... ADD LRAS LRAS LCBR CLK PRELIMINARY (July, 2005, Version 0.1) Data Input Register 512K X 16 512K X 16 Column Decoder Latency & Burst Length Programming Register LCAS LWE Timing Register CKE CS RAS CAS 2 A43E06161 LDQM LWCBR L(U)DQM WE AMIC Technology, Corp. LWE LDQM DQi ...
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... Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +1.7V~1.95V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 3 A43E06161 Description AMIC Technology, Corp. ...
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... -1 Min Typ 2.0 2.0 WE CAS , , , 3.5 = -25ºC to +70ºC or -40ºC to +85ºC) Max Unit 1.95 V 1.95 V VDD+0 0.2 V µ µ A 1.5 See Figure 1 AMIC Technology, Corp. A43E06161 Max Unit 4.0 pF 4.0 pF 6.0 pF Note Note -0.1mA 0.1mA OL Note 2 Note 3 ...
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... CCD CCD ≥ (min CKE ≤ 0.2V CKE ≤ 0.2V 5 Value 0.1 + 0.01 DC1 0.1 + 0.01 DC2 Speed CAS Latency -75 -95 20 0.3 0.1 = 15ns 5 = ∞ 15ns 200 10 (min). CC (min). CC AMIC Technology, Corp. A43E06161 Unit µ F µ F Unit Notes µ A µ A ...
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... AC Output Load Circuit -95 Max Min Max 9.5 1000 1000 *All AC parameters are measured from half to half. AMIC Technology, Corp. A43E06161 Unit 0.5V x VDDQ Unit Note 1 ...
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... Minimum delay is required to complete write. 3. All parts allow every cycle column address change. PRELIMINARY (July, 2005, Version 0.1) Version -75 - 28 100 84 85.5 7.5 8 7.5 9.5 7.5 9.5 AMIC Technology, Corp. 7 A43E06161 Unit Note CLK µ CLK ...
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... Exit Valid Don’t Care Logic High Logic Low) 8 A43E06161 WE DQM BA A10/ A9~ CODE Row Addr. L Column Addr. ...
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... Reserved Burst Length Burst Length Type BT=0 Sequential Interleave Reserved Reserved Reserved 256(Full) AMIC Technology, Corp. A43E06161 A1 A0 BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved (Note 3) ...
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... A43E06161 Interleave Interleave ...
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... RCD the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the 11 A43E06161 CAS and BA in the ...
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... RAS RP with high on A10/AP after both banks have satisfied RAS CS , and CAS . The auto refresh command can only be asserted with AMIC Technology, Corp. A43E06161 DQM operation is ” is defined as the RP ” with clock cycle RP the bank activate ...
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... To enter the Deep Power Down Mode all banks must be precharged and the necessary Precharged Delay t occur. and CKE with high on 13 A43E06161 ” before the SDRAM reaches idle RC must RP AMIC Technology, Corp. ...
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... DQM masks both data-in and data-out. PRELIMINARY (July, 2005, Version 0.1) 2) Clock Suspended During Read (BL= Read Mask (BL=4) RD Hi-Z Hi Hi-Z Hi Masked by CKE Suspended Dout Masked by CKE Hi Hi DQM to Data-out Mask = AMIC Technology, Corp. A43E06161 Q3 ...
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... Version 0.1) Note 1 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 DQ(CL2) DQ(CL3) CAS access; read, write and block write Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 QB1 DA0 QB0 t CDL Note3 AMIC Technology, Corp. A43E06161 QB1 ...
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... To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. PRELIMINARY (July, 2005, Version Note Hi Hi Note AMIC Technology, Corp. A43E06161 ...
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... Version 0.1) Note 2 PRE Note Masked by DQM PRE RDL PRE Note 1 Auto Precharge Starts Note 1 Auto Precharge Starts CAS interrupt of the same/another bank is illegal. 17 A43E06161 from this point. RP AMIC Technology, Corp. ...
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... Version 0.1) 2) Write Burst Stop (BL=8) PRE Note 1 RDL 4) Read Burst Stop (BL=4) PRE Note DQ(CL2 DQ(CL3) MRS ACT t 1CLK RP 18 CLK CMD WR STOP (note 2) BDL CLK CMD RD STOP AMIC Technology, Corp. A43E06161 Note ...
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... Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended. PRELIMINARY (July, 2005, Version 0.1) 2) Power Down (=Precharge Power Down) Exit CLK CKE t SS Internal Note 2 CLK NOP ACT CMD Note 5 CMD CMD t RC AMIC Technology, Corp. A43E06161 ...
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... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 20 A43E06161 CAS interrupt can not be issued. AMIC Technology, Corp. ...
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... DQM High level is necessary High-Z DQ Precharge Auto Refresh (All Banks) PRELIMINARY (July, 2005, Version 0. Auto Refresh KEY KEY KEY Mode Regiser Set AMIC Technology, Corp. A43E06161 Row Active (A-Bank) : Don't care ...
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... SH *Note 2,3 *Note 2 *Note 3 *Note SAC SLZ SHZ Read Write *Note 4 *Note *Note Row Active Precharge AMIC Technology, Corp. A43E06161 Don't care ...
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... Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. BA Precharge 0 Bank A 1 Bank B X Both Bank 23 A43E06161 AMIC Technology, Corp. ...
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... OH Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD SAC 24 A43E06161 Cb0 Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write Precharge (A-Bank) AMIC Technology, Corp ...
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... High Cb0 Cc0 *Note 2 *Note1 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Dc0 Write Read (A-Bank) (A-Bank) before Row precharge, will be written. RDL 25 A43E06161 *Note 2 Cd0 t RDL t CDL *Note3 Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 Write Precharge ...
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... CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Read Read Read (A-Bank) (B-Bank) (A-Bank) AMIC Technology, Corp. A43E06161 *Note 2 Precharge (A-Bank) : Don't care ...
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... RBb CBb RBb DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 t CDL Row Active Write (B-Bank) (B-Bank *Note 2 CAc CBd DAc1 DBd0 DBd1 t RDL *Note 1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) AMIC Technology, Corp. A43E06161 Don't care ...
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... Precharge (A-Bank) Row Active (B-Bank CBb RAc CAc RAc t CDL *Note 1 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write Read (B-Bank) (A-Bank) Row Active (A-Bank) AMIC Technology, Corp. A43E06161 QAc0 QAc1 QAc2 QAc0 QAc1 : Don't care ...
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... QAa0 QAa1 QAa2 Read with Auto Precharge Start Point (A-Bank) (A-Bank CBb DBb0 DBb1 DBb2 DBb3 QAa3 DBb0 DBb1 DBb2 DBb3 Write with Auto Precharge (B-Bank) AMIC Technology, Corp. A43E06161 Auto Precharge Start Point (B-Bank) : Don't care ...
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... Auto Precharge Strart Point (A-Bank) *Note 1 after A Bank auto precharge starts Qb3 Qb2 Qb3 Precharge Row Active (B-Bank) (A-Bank) AMIC Technology, Corp. A43E06161 Da0 Da1 Da0 Da1 Write with Auto Precharge (A-Bank) : Don't care ...
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... Qa2 * Note 1 Auto Precharge Auto Precharge Start Point (A-Bank) (A-Bank) Row Active (B-Bank Qb0 Qb1 Qb2 Qb3 Qa3 Qb0 Qb1 Db2 Read with Auto Precharge Start Point (B-Bank) (B-Bank) AMIC Technology, Corp. A43E06161 Db3 : Don't care ...
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... QAa1 QAa2 QAa3 QAa4 QAa0 2 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 Precharge (A-Bank) RAS interrupt. AMIC Technology, Corp. A43E06161 QAb4 QAb5 : Don't care ...
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... Version 0. High CAb * Note 1 t BDL * Note 2 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 Write Burst Stop (A-Bank RDL * Note 3 DAb4 DAb5 AMIC Technology, Corp. A43E06161 18 19 Precharge (A-Bank) : Don't care ...
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... Row Active Row Active (B-Bank) Read with Auto Precharge (A-Bank Note 2 RAc CBc CAd RAc DBc0 QAd0 DBc0 Read (A-Bank) (A-Bank) Write with Auto Precharge (B-Bank) AMIC Technology, Corp. A43E06161 QAd1 QAd0 QAd1 Precharge (A-Bank) : Don't care ...
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... Note : DQM needed to prevent bus contention. PRELIMINARY (July, 2005, Version 0. Qa0 Qa1 Qa2 Qa3 t SHZ Clock Read Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write Read DQM DQM Clock Write Suspension AMIC Technology, Corp. A43E06161 Don't care ...
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... Version 0. Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command Qa0 Qa1 Qa2 Read Precharge AMIC Technology, Corp. A43E06161 Don't care ...
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... If the system uses burst refresh. PRELIMINARY (July, 2005, Version 0. Note 4 * Note 3 Hi-Z Self Refresh Exit min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Corp. A43E06161 Don't care ...
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... Please refer to Mode Register Set table. PRELIMINARY (July, 2005, Version 0.1) Auto Refresh Cycle Auto Refresh WE activation at the same clock cycle with address key will set internal mode register. RAS activation. 38 A43E06161 High t RC Hi-Z AMIC Technology, Corp ...
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... Deep Power Down Mode Entry CLK CKE CS WE CAS RAS ADDR DQM DQ input DQ output PRELIMINARY (July, 2005, Version 0.1) High Precharge Command Deep Power Down Entry Normal Mode Deep Power Down Mode 39 A43E06161 AMIC Technology, Corp. ...
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... Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register PRELIMINARY (July, 2005, Version 0. All Banks Auto Precharge Refresh Refresh Mode Extended Auto Register Mode Set Register Set AMIC Technology, Corp. A43E06161 New Command Accepted Here ...
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... ILLEGAL NOP(Continue Burst to End → Precharge NOP(Continue Burst to End → Precharge ILLEGAL H BA CA,A10/AP ILLEGAL L BA CA,A10/AP ILLEGAL X BA RA, PA ILLEGAL ILLEGAL 41 A43E06161 Action Note AMIC Technology, Corp ...
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... NOP → Idle after NOP → Idle after ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address 42 A43E06161 Action RCD RCD Auto Precharge PA = Precharge All AMIC Technology, Corp. Note ...
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... Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 43 A43E06161 Action RC RC (min) has to be elapse after CKE’s low to RC AMIC Technology, Corp. Note ...
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... Ordering Information Part No. Min. Cycle Time A43E06161V-75 A43E06161V-75F A43E06161V-75U A43E06161V-75UF A43E06161V-95 A43E06161V-95F A43E06161V-95U A43E06161V-95UF Note for industrial operating temperature range -40ºC to +85ºC. PRELIMINARY (July, 2005, Version 0.1) Max. Clock Frequency (ns) (MHz) 7.5 133 7.5 133 7.5 133 7.5 133 9.5 105 9.5 105 9.5 105 9.5 105 44 A43E06161 ...
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... E 0.396 0.400 0.404 10. 0.031 - L 0.016 0.020 0.024 θ 0° - 5° 45 unit: inches/mm Detail "A" R0.15 REF. R0.15 REF. θ Detail "A" Dimensions in mm Min Nom Max - - 1.20 0. 0.95 1.016 1.05 0.30 - 0.45 0.12 - 0.21 20.955 21.055 11.76 11.96 10.16 10.26 - 0.800 - 0.40 0.50 0.60 0° - 5° AMIC Technology, Corp. A43E06161 ...