A43L2616-PH Series AMIC Technology, Corp., A43L2616-PH Series Datasheet - Page 25

• Manufacturer Part Number: A43L2616-PH Series
• Description: 1M x 16 Bit x 4 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Read & Write Cycle at Same Bank @Burst Length=4
(May, 2002, Version 0.0)
(CL = 2)
(CL = 3)
CLOCK
A10/AP
ADDR
CKE
RAS
CAS
BS0
BS1
DQM
DQ
CS
DQ
WE
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
3. Access time from Row address. t
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
1
enters precharge. Last valid output will be Hi-Z after t
2
t
RCD
*Note 3
*Note 3
t
RAC
3
t
(A-Bank)
RAC
Ca0
Read
4
t
SAC
5
t
SAC
t
OH
Qa0
t
RC
6
t
*Note 1
OH
Qa1
Qa0
CC
7
*(t
RCD
Qa2
Qa1
8
*Note 2
t
SHZ
Precharge
+ CAS latency-1) + t
(A-Bank)
Qa3
Qa2
9
t
SHZ
High
Qa3
25
*Note 4
SHZ
10
from the clock.
*Note 4
11
Row Active
(A-Bank)
SAC
Rb
Rb
12
13
14
(A-Bank)
Db0
Write
Cb0
Db0
A43L2616-PH Series
15
AMIC Technology, Inc.
Db1
Db1
16
Db2
Db2
17
t
t
RDL
RDL
Db3
Db3
18
: Don't care
19
Precharge
(A-Bank)