MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 96

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Layout Practices
4.5 Layout Practices
4-4
Each
power supply. Similarly, each
power supply pins drive distinct groups of logic on the chip. The
to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of
the package. The capacitor leads and associated printed circuit traces connecting to chip
GND
employing two inner layers as
All output pins on the MSC8102 have fast rise and fall times. Printed circuit board (PCB) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data
busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should
consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB
layout and bypassing becomes especially critical in systems with higher capacitive loads because these
loads create higher transient currents in the
signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins.
There is one pair of PLL supply pins:
to the
place the circuit as close as possible to
followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10- resistor to
should be kept short and direct.
GND
V
bypass
CCSYN
SYN
V
should be kept to less than half an inch per capacitor lead. A four-layer board is recommended,
V
CC
GND
CCSYN
by a 0.01-µF capacitor located as close as possible to the chip package. The user should also
should be provided with an extremely low impedance path to ground and should be bypassed to
and
SYN
V
input with a circuit similar to the one in Figure 4-3. To filter as much noise as possible,
DD
to
pin on the MSC8102 should be provided with a low-impedance path to the board
V
CCSYN
V
DD
with a 0.01-µF capacitor as close as possible to the chip package
10
GND
V
CC
and
pin should be provided with a low-impedance path to ground. The
Figure 4-3. V
V
CCSYN
V
GND
10nH
CCSYN
V
CC
-
planes.
10 µF
GND
. The 0.01-µF capacitor should be closest to
,
V
DD
SYN
CCSYN
, and
. To ensure internal clock stability, filter the power
GND
Bypass
circuits. Pull up all unused inputs or
V
CC
0.01 µF
power supply should be bypassed
V
CCSYN
V
DD
V
. These traces
CC
V
,
CCSYN
V
DD
, and
,