MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 17

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Signal Name
ARTRY
D[0–31]
Reserved
DP0
DREQ1
EXT_BR2
IRQ1
DP1
DACK1
EXT_BG2
IRQ2
DP2
DACK2
EXT_DBG2
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input/
Input/
Input/
Input/
Input/
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Input
Input
Address Retry
Assertion of this signal indicates that the bus master should retry the bus transaction. An
external master asserts this signal to enforce data coherency with its caches and to
prevent deadlock situations.
Data Bus Bits 0–31
In write transactions, the bus master drives the valid data on this bus. In read transactions,
the slave drives the valid data on this bus.
The primary configuration selection (default after reset) is reserved.
System Bus Data Parity 0
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 0 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 0 and D[0–7].
DMA Request 1
Used by an external peripheral to request DMA service.
External Bus Request 2
An external master asserts this pin to request bus ownership from the internal arbiter.
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
System Bus Data Parity 1
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 1 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 1 and D[8–15].
DMA Acknowledge 1
The DMA drives this output to acknowledge the DMA transaction on the bus.
External Bus Grant 2
The MSC8102 asserts this pin to grant bus ownership to an external bus master.
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
System Bus Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 2 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 2 and D[16–23].
DMA Acknowledge 2
The DMA drives this output to acknowledge the DMA transaction on the bus.
External Data Bus Grant 2
The MSC8102 asserts this pin to grant data bus ownership to an external bus master.
Direct Slave Interface, System Bus, and Interrupt Signals
2
2
Description
1-9