MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 39

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

PORESET
PORESET
Input
HRESET
Output (I/O)
SRESET
Output (I/O)
No.
Internal
5
6
Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus
•
•
•
Delay from SPLL and DLL lock to SRESET
de-assertion
•
•
Delay from SPLL and DLL lock to HRESET
de-assertion
REFCLK = 75 Mhz
DLL disabled
REFCLK = 75 Mhz
REFCLK = 75 Mhz
DLL disabled
REFCLK = 75 Mhz
DLL enabled
REFCLK = 18 Mhz
REFCLK = 18 Mhz
DLL enabled
REFCLK = 18 Mhz
REFCLK = 18 Mhz
1
Figure 2-1. Timing Diagram for a Reset Configuration Write
Characteristics
Reset configuration write
sequence occurs during this
period.
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1-2]
pins are sampled
Reset Configuration
Host programs
1 + 2
Word
2
SPLL and DLL
locking period.
When DLL is disabled,
reset period is shortened
by 3073 bus clocks.
MODCK[3–5],
DLLDIS bits
are ready for SPLL.
3585 / REFCLK
3588 / REFCLK
512 / REFCLK
515 / REFCLK
Expression
3 + 4
Min
199.17
199.33
SPLL and DLL are locked
(no external indication)
47.84
28.61
47.5
28.4
6.83
6.87
Max
5
6
AC Timings
Unit
s
s
s
s
s
s
s
s
2-9