MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 36

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2.6.3 Reset Timing
2-6
The MSC8102 has several inputs to the reset logic:
• Power-on reset (
• External hard reset (
• External soft reset (
• Software watchdog reset
• Bus monitor reset
• Host reset command through JTAG
All MSC8102 reset sources are fed into the reset controller, which takes different actions depending on
the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table
2-8 describes the reset sources.
CLKIN
•
•
DLLIN
•
•
Reference Clock (REFCLK)
•
•
Output Clock (CLKOUT)
•
•
SC140 core clock
•
•
Notes:
Power-on reset
(PORESET)
External Hard
reset
(HRESET)
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Name
1
1
1.
2.
Characteristics
The rise and fall time of external clocks should be 5 ns maximum
Measured at 50 percent of the input transition.
Direction
Output
Input/
PORESET
Input
SRESET
HRESET
Initiates the power-on reset flow that resets the MSC8102 and configures various
attributes of the MSC8102. On PORESET, the entire MSC8102 device is reset. SPLL
and DLL states are reset, HRESET and SRESET are driven, the SC140 extended
cores are reset, and system configuration is sampled. The clock mode (MODCK bits),
reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a
System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8102. While
HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon
hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset,
and system configuration is sampled. The most configurable features are reconfigure.
These features are defined in the 32-bit hard reset configuration word described in
Hard Reset Configuration Word section of the Reset chapter in the MSC8102
Reference Manual.
)
)
)
Table 2-7. Clock Operation
Table 2-8. Reset Sources
Symbol
F
T
F
T
F
T
F
T
F
T
REFCLK
REFCLK
CLKOUT
CLKOUT
CLKIN
CLKIN
CORE
CORE
DLLIN
DLLIN
166.7 MHz
33.3 MHz
33.3 MHz
33.3 MHz
36 MHz
13.3 ns
13.3 ns
12 ns
12 ns
Min
250 MHz Device
4 ns
Description
83.3 MHz
83.3 MHz
250 MHz
75 MHz
75 MHz
28 ns
30 ns
30 ns
30 ns
Max
6 ns
166.7 MHz
33.3 MHz
33.3 MHz
33.3 MHz
36 MHz
13.3 ns
13.3 ns
10.9 ns
10.9 ns
3.6 ns
Min
275 MHz Device
91.7 MHz
91.7 MHz
275 MHz
75 MHz
75 MHz
28 ns
30 ns
30 ns
30 ns
Max
6 ns