MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 42

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MSC8102D

Manufacturer Part Number
MSC8102D
Description
Quad Core 16-Bit Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
AC Timings
2-12
Note:
No.
32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge
32b BADDR delay from REFCLK rising edge
33a Data bus delay from REFCLK rising edge
33b DP delay from REFCLK rising edge
31
34
35
36
PSDVAL/TEA/TA delay from REFCLK rising edge
Memory controller signals/ALE delay from REFCLK rising edge
DBG/BR/ABB/CS delay from REFCLK rising edge
Delay from REFCLK rising edge for all other signals
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL outputs
Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs
Table 2-16. AC Timing for SIU Outputs for 50 pF in Pipelined Mode
AACK/ARTRY/TA/TEA/DBG/BG/BR/PSDVAL inputs
Data bus inputs—ECC and parity modes
Characteristic
Data bus inputs—normal mode
All other normal mode outputs
Memory controller/ALE signals
PSDVAL/TEA/TA outputs
Figure 2-3. Bus Signal Timing
Data bus outputs
DBG/BR/ABB/CS
All other inputs
DP outputs
DP inputs
BADDR
REFCLK
11
12
13
14
15
16
32a
32b
33a
33b
34
35
36
Minimum Maximum
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
31
10
10
10
10
9.5
8.5
9
8
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns

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