MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 5

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

• Direct Slave Interface (DSI) that provides a 32/64-bit wide slave host interface. It is part of a
• Multi-channel DMA controller:
• External interfaces and control modules managed on the internal peripheral bus (IPBus) by an IP
• Up to four independent TDM modules, each with the following features:
dual-system bus architecture shared with the external system bus. The dual architecture allows the DSI
data bus to be 32 or 64 bits wide and the system data bus to be 64 or 32 bits wide, respectively. It
operates only as a slave device under the control of an external host processor.
— 16 time-multiplexed unidirectional channels with infrastructure of 32 channels.
— Services up to four external peripherals.
— Supports DONE or DRACK protocol on two external peripherals.
— Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO
— Priority-based time-multiplexing between channels using 16 internal priority levels
— A flexible channel configuration:
— Flyby transfers in which a single data access is transferred directly from the source to the
master device, including:
— Four time-division multiplexing (TDM) modules, each supporting up to 64 channels (256 channels
— RS-232 interface/universal asynchronous receiver/transmitter (UART)
— Two 16-timer modules (32 timers total)
— Eight hardware semaphore registers used by external hosts to control shared resources and ensure
— Thirty-two general-purpose input/output (GPIO) signals
— Global interrupt controller (GIC) to handle external interrupt functions (input and output)
— Either totally independent receive and transmit, each having one data line, one clock line, and one
— Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses.
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generates:
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destination without using a DMA FIFO.
total)
data coherency
frame sync line or four data lines, one clock and one frame sync that are shared between the
transmit and receive.
32-bit address decoding with programmable mask.
Variable block sizes (32 KB to 4 GB).
Selectable memory controller machine.
Two types of data errors check/correction (on 60x-compatible system bus only): Normal
odd/even parity and Read-modify-write (RMW) odd/even parity for single accesses.
Write-protection capability.
Control signal generation machine selection on a per-bank basis.
Flexible chip-select assignment between the 60x-compatible system bus and local bus.
Support for internal or external masters on the 60x-compatible system bus.
Data buffer controls activated on a per-bank basis.
Atomic operation.
RMW data parity check (on 60x-compatible system bus only).
Extensive external memory-controller/bus-slave support.
Parity byte select signal, which enables a fast, glueless connection to RMW-parity devices (on
60x-compatible system bus only).
Data pipeline to reduce data set-up time for synchronous devices.
a watermark request to indicate that the FIFO contains data for the DMA to empty and write
to the destination
a hungry request to indicate that the FIFO can accept more data.
All channels support all features.
All channels connect to the 60x-compatible system bus or local bus.
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