MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 6

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

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• UART
— Hardware A-law/ -law conversion
— Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are
— Up to 256 channels.
— Up to 16 MB per channel buffer (granularity 8 bytes), where A/ law buffer size is double
— Receive buffers share one global write offset pointer that is written to the same offset relative to
— Transmit buffers share one global read offset pointer that is read from the same offset relative to
— All channels share the same word size.
— Two programmable receive and two programmable transmit threshold levels with interrupt
— Each channel can be programmed to be active or inactive.
— 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels,
— The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.
— Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the
— Frame sync can be programmed as active low or active high.
— Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.
— MSB or LSB first support.
— Two signals for transmit data and receive data.
— No clock, asynchronous mode.
— Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system
— Full-duplex operation.
— Standard mark/space non-return-to-zero (NRZ) format.
— 13-bit baud rate selection.
— Programmable 8-bit or 9-bit data format.
— Separately enabled transmitter and receiver.
— Programmable transmitter output polarity.
— Two receiver wakeup methods:
— Separate receiver and transmitter interrupt requests.
— Eight flags, the first five can generate interrupt request:
— Receiver framing error detection.
— Hardware parity checking.
— 1/16 bit-time noise detection.
— Maximum bit rate 6.25 Mbps.
used, 12.5 MHz if four data lines are used).
(granularity 16 byte)
their start address.
their start address.
generation that can be used, for example, to implement double buffering.
respectively.
falling edge of the clock.
bus or on the DSI.
°
°
°
°
°
°
°
°
°
°
Idle line wakeup.
Address mark wakeup.
Transmitter empty.
Transmission complete.
Receiver full.
Idle receiver input.
Receiver overrun.
Noise error.
Framing error.
Parity error.