MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 35

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.6 AC Timings
2.6.1 Load Assumptions
2.6.2 Clock and Timing Signals
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs
and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and a 50
line. For any additional pF, add 0.07 ns for the delay and take the RC delay into consideration.
The following sections include a description of clock signal characteristics.
Table 2-6 shows the maximum frequency values for internal (Core, Reference, and DSI) and external
(CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded.
Phase jitter between CLKOUT and DLLIN
CLKIN frequency
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Note:
Core Frequency
Reference Frequency (REFCLK)
DSI Clock Frequency (HCLKIN)
External Clock Output Frequency (CLKOUT)
Note:
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the
frequency after predivider (SPLLMFCLK) higher than 18 MHz
The REFCLK is CLKOUT.
Characteristic
Characteristic
Table 2-5. System Clock Parameters
Table 2-6. Maximum Frequencies
Minimum
36
—
—
—
—
—
if REFCLK
(0.01
if REFCLK > 70 MHz, HCLKIN = 70 MHz
CLKOUT) + CLKIN jitter
Maximum
Maximum in MHz
70 MHz, HCLKIN = CLKOUT
0.5
75
5
2
5
83.3/91.7
83.3/91.7
250/275
AC Timings
transmission
Unit
MHz
ns
ns
ns
ns
ns
2-5