MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 16

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Direct Slave Interface, System Bus, and Interrupt Signals
1-8
Signal Name
IRQ5
BADDR29
BADDR28
BADDR27
BR
BG
DBG
ABB
IRQ4
DBB
IRQ5
TS
AACK
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input/
Input/
Input/
Input/
Input/
Input/
Input/
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Bus Burst Address 29
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
Burst Address 28
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
Burst Address 27
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
Bus Request
When an external arbiter is used, the MSC8102 asserts this pin as an output to request
ownership of the bus. When the MSC8102 controller is used as an internal arbiter, an
external master asserts this pin as an input to request bus ownership.
Bus Grant
When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant bus
ownership to an external bus master. When an external arbiter is used, it asserts this pin
as an input to grant bus ownership to the MSC8102.
Data Bus Grant
When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant data
bus ownership to an external bus master. When an external arbiter is used, it asserts this
pin as an input to grant data bus ownership to the MSC8102.
Address Bus Busy
The MSC8102 asserts this pin as an output for the duration of the address bus tenure.
Following an AACK, which terminates the address bus tenure, the MSC8102 deasserts
ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8102 does not
assume bus ownership as long as it senses this pin is asserted as an input by an external
bus master.
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Data Bus Busy
The MSC8102 asserts this pin as an output for the duration of the data bus tenure.
Following a TA, which terminates the data bus tenure, the MSC8102 deasserts DBB for a
fraction of a bus cycle and then stops driving this pin. The MSC8102 does not assume
data bus ownership as long as it senses that this pin is asserted as an input by an external
bus master.
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Bus Transfer Start
Assertion of this pin signals the beginning of a new address bus tenure. The MSC8102
asserts this signal when one of its internal bus masters begins an address tenure. When
the MSC8102 senses that this pin is asserted by an external bus master, it responds to the
address bus tenure as required (snoop if enabled, access internal MSC8102 resources,
memory controller support).
Address Acknowledge
A bus slave asserts this signal to indicate that it has identified the address tenure.
Assertion of this signal terminates the address tenure.
2
2
1
2
1
1
1
Description