TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 86

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

9.3 Configuring Control and Data Registers
TC7DRA
TC7DRB
TC7DRC
TC7DRA
TC7DRB
TC7DRC
Execute write
instruction.
Data valid
in each
period
Configure control and data registers in the following order:
Valid in next
period
A1
B1
C1
1. Configure mode settings: TC7CR1, TC7CR2
2. Configure data registers (Dead time, pulse width):
3. Configure data registers (Period): TC7DRC
4. Configure timer start/stop:TC7CR3
Execute write
instruction.
TC7DRA, TC7DRB, TC7DRD, TC7DRE (only those required for selected mode)
A1
B1
C1
• Data registers have double-stage configuration, consisting of a data register that stores data written by
• Data stored in a data register is processed according to the output mode specified in the TC7OUT,
• Data registers required for the specified output mode are used for data register processing and transfer
• Writing data to the upper byte of the TC7DRC causes a data transfer request to be issued for data in
• If a data register is written more than once within a period, the data in the data register that was set
If data is rewritten more
than once within a
period, the data written
first is valid in the next
period.
Figure 9-2 Example Configuration of Control/data Registers (1)
an instruction and a compare register to be compared with the counter.
transferred to the compare register, and then used for comparison with the up counter.
to the compare register. Ensure that the output mode is specified in the TC7OUT (Bits 0 and 1 of the
TC7CR2) before configuring data registers.
data registers TC7DRA to TC7DRE. If a counter match or clear occurs while that request is valid, the
data is transferred to the compare register and becomes valid for comparison.
when the upper byte of the TC7DRC was written is valid as data for the next period. The data in the
data register written last in the first period will be valid for the period that follows the next period.
A2
C2
A1
B1
C1
Execute more than one
data write instruction.
Period (1)
C3
Execute write
instruction.
Period (1)
A2
B2
C2
B2
C4
A3
C5
If data is rewritten more than
once within a period, the data
written last is valid in the
period following the next
period.
Execute write instruction.
A2
B1
C2
A4
C6
Period (2)
Period (2)
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A5
C7
Previous data is
maintained if data is not
rewritten within the period.
A3
B2
C5
No data write
Execute write
instruction.
Period (3)
Period (3)
A3
B3
C3
Execute write instruction.
A6
B3
C8
A5
B2
C7
Period (4)
Period (4)
A7
B4
C9
TMP86CH12MG
A6
B3
C8
Period (5)