TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 54

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TMP86xy12MG

Manufacturer Part Number
TMP86xy12MG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy12MG

Package
SSOP30
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
16
Ram Size
512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
-
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
8
Da Converter Channels
-
Timer Counter 18-bit Channel
IGBT
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
24
Power Supply (v)
4.5 to 5.5
4. Special Function Register (SFR)
4.1 SFR
formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
TMP86CH12MG.
The TMP86CH12MG adopts the memory mapped I/O system, and all peripheral control and data transfers are per-
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
Address
000CH
000DH
001CH
001DH
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000EH
000FH
0010H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
001EH
001FH
0020H
0021H
0022H
0023H
0024H
0025H
0011H
ADCDR2
ADCDR1
UARTSR
P0PRD
P2PRD
Read
Page 43
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P0OUTCR
TC7DRAH
TC7DRBH
TC7DRCH
TC1DRAH
TC1DRBH
TC7DRAL
TC7DRBL
TC7DRCL
TC1DRAL
TC1DRBL
PWREG3
PWREG4
Reserved
Reserved
Reserved
Reserved
Reserved
ADCCR1
TTREG3
TTREG4
RTCCR
TC1CR
TC3CR
TC4CR
P3CR1
P3CR2
P0DR
P1DR
P2DR
P3DR
P1CR
UARTCR1
UARTCR2
Write
-
-
-
-
TMP86CH12MG

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