TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 18

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

2. Operational Description
2.1 CPU Core Functions
2.1.1 Memory Address Map
2.1.2 Program Memory (MaskROM)
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
memory address map.
The TMP86CH12MG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special
The TMP86CH12MG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ).
MaskROM
RAM
DBR
SFR
FFBF
FFC0
FFDF
FFA0
FFE0
FFFF
0FFF
C000
003F
023F
0F80
0000
0040
H
H
H
H
H
H
H
H
H
H
H
H
H
Figure 2-1 Memory Address Map
64 bytes
16384
bytes
bytes
bytes
512
128
Page 7
Vector table for interrupts
(32 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for interrupts
(32 bytes)
MaskROM:
RAM:
DBR:
SFR:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
Data buffer register includes:
Peripheral control registers
Peripheral status registers
Program memory
TMP86CH12MG
TMP86CH12MG