TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 59

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

5.1 Port P0 (P07 to P00)
5.1 Port P0 (P07 to P00)
Table 5-1 Register Programming for Multi-function Ports (P07 to P00)
Port input, external interrupt input, serial interface input, timer counter input or UART input
Port “0” output
Port “1” output, serial interface output or UART output
Timer counter 7 output
timer/counter input/output.
P0OUTCR. During reset, the P0DR is initialized to "1", and the P0OUTCR is initialized to "0". When a correspond-
ing bit of P0OUTCR is "0". the output circuit is selected to a sink open drain and when a corresponding bit of
P0OUTCR is "1", the output circuit is selected to a C-MOS output.
input , the corresponding output control (P0OUTCR) should be set to "0" after P0DR is set to "1".
Next, set the PPG output initial value in the PPG1INI and/or PPG2INI, and set the PPG1OE and/or PPG2OE to "1"
to enable PPG output. At this time, the output latch (P0DR) should be set to the same value as the PPG output initial
value in the PPG1INI, PPG2INI.
should be read.
Port P0 is an 8-bit input/output port.
Port P0 is also used as an external interrupt input, a serial interface input/output, an UART input/output and a
When used as an input port, an external interrupt input, a serial interface input ,an UART input and a timer/counter
When using this port as a PPG1 and/or PPG2 output, set the output latch (P0DR), and then set the P0OUTCR.
P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address.
When read the output latch data, the P0DR should be read. When read the terminal input data, the P0PRD register
It can be selected whether output circuit of P0 port is a C-MOS output or a sink open drain individually, by setting
During reset, the P0DR is initialized to "1", and the P0OUTCR is initialized to "0".
Function
Page 48
Set to the same value as
PPG1INI and PPG2INI
P0DR
“1”
“0”
“1”
Programmed Value
Programming for each
TMP86CH12MG
applications
P0OUTCR
“0”